M68HC128 Datasheet, PDF (276/362 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
msCAN12 Controller
16.8 Timer Link
The msCAN12 generates a timer signal whenever a valid frame has been received.
Because the CAN specification defines a frame to be valid if no errors occurred
before the EOF field has been transmitted successfully, the timer signal is
generated right after the EOF. A pulse of one bit time is generated. As the
msCAN12 receiver engine also receives the frames being sent by itself, a timer
signal also is generated after a successful transmission.
The previously described timer signal can be routed into the on-chip timer interface
module (TIM). This signal is connected to the timer n channel m input⁽¹⁾ under the
control of the timer link enable (TLNKEN) bit in the CMCR0.
After timer n has been programmed to capture rising edge events, it can be used
under software control to generate 16 bit-time stamps which can be stored with the
received message.
16.9 Clock System
Figure 16-7 shows the structure of the msCAN12 clock generation circuitry. With
this flexible clocking scheme the msCAN12 is able to handle CAN bus rates
ranging from 10 kbps to 1 Mbps.
CGM
SYSCLK
EXTALi
CLKSRC
MSCAN12
CGMCANCLK
PRESCALER
(1...64)
TIME QUANTA
CLOCK
CLKSRC
Figure 16-7. Clocking Scheme
The clock source bit (CLKSRC) in the msCAN12 module control register (CMCR1)
(see 16.12.3 msCAN12 Bus Timing Register 0) defines whether the msCAN12
is connected to the output of the crystal oscillator (EXTALi) or to a clock twice as
fast as the system clock (ECLK).
The clock source has to be chosen so that the tight oscillator tolerance
requirements (up to 0.4 percent) of the CAN protocol are met. Additionally, for high
CAN bus rates (1 Mbps), a 50 percent duty cycle of the clock is required.
Data Sheet
276
1. The timer channel being used for the timer link is integration dependent.
msCAN12 Controller
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M68HC12B Family — Rev. 9.0
MOTOROLA