M68HC128 Datasheet, PDF (233/362 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Byte Data Link Communications (BDLC)
BDLC MUX Interface
impedance. This allows the communication path through the analog transceiver to
be tested without interfering with network activity. Using the BDLC analog loopback
mode in conjunction with the analog transceiver’s loopback mode ensures that,
once the off-chip analog transceiver has exited loopback mode, the BDLC does not
begin communicating before a known condition exists on the J1850 bus.
15.7 BDLC MUX Interface
The MUX (multiplex) interface is responsible for bit encoding/decoding and digital
noise filtering between the protocol handler and the physical interface.
15.7.1 Rx Digital Filter
The receiver section of the BDLC includes a digital low-pass filter to remove narrow
noise pulses from the incoming message. An outline of the digital filter is shown in
Figure 15-3.
RX DATA
FROM
PHYSICAL
INTERFACE
(BDRXD)
INPUT
SYNC
DQ
4-BIT UP/DOWN COUNTER
UP/DOWN
OUT
DATA
LATCH
DQ
FILTERED
RX DATA OUT
MUX
INTERFACE
CLOCK
Figure 15-3. BDLC Rx Digital Filter Block Diagram
15.7.1.1 Operation
The clock for the digital filter is provided by the MUX interface clock (see f_BDLC
parameter in Table 15-2). At each positive edge of the clock signal, the current
state of the receiver physical interface (BDRxD) signal is sampled. The BDRxD
signal state is used to determine whether the counter should increment or
decrement at the next negative edge of the clock signal.
The counter increments if the input data sample is high but decrements if the input
sample is low. Therefore, the counter progresses either up toward 15 if, on
average, the BDRxD signal remains high or progresses down toward 0 if, on
average, the BDRxD signal remains low.
M68HC12B Family — Rev. 9.0
MOTOROLA
Byte Data Link Communications (BDLC)
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Data Sheet
233