M68HC128 Datasheet, PDF (250/362 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Byte Data Link Communications (BDLC)
Table 15-2. BDLC Rate Selection
f_XCLK Frequency
R1
1.049 MHz
0
2.097 MHz
0
4.194 MHz
1
8.389 MHz
1
1.000 MHz
0
2.000 MHz
0
4.000 MHz
1
8.000 MHz
1
R0
Division
0
1
1
2
0
4
1
8
0
1
1
2
0
4
1
8
f_BDLC
1.049 MHz
1.049 MHz
1.049 MHz
1.049 MHz
1.00 MHz
1.00 MHz
1.00 MHz
1.00 MHz
IE — Interrupt Enable Bit
This bit determines whether the BDLC generates CPU interrupt requests in run
mode. It does not clear BSVR interrupts when exiting the BDLC stop or BDLC
wait modes. Interrupt requests are maintained until all of the interrupt request
sources are cleared by performing the specified actions upon the BDLC’s
registers (or an MCU reset sets BSVR bits to $00). Interrupts that were pending
at the time that this bit is cleared may be lost.
If the programmer does not want to use the interrupt capability of the BDLC, the
BDLC state vector register (BSVR) can be polled periodically to determine
BDLC states.
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
WCM — Wait Clock Mode Bit
This bit determines the operation of the BDLC during CPU wait mode.
0 = Run BDLC internal clocks during CPU wait mode.
1 = Stop BDLC internal clocks during CPU wait mode.
15.9.2 BDLC Control Register 2
Address: $00FA
Bit 7
6
5
4
3
2
1
Read:
ALOOP
Write:
DLOOP
RX4XE
NBFS
TEOD
TSIFR TMIFR1
Reset: 1
1
0
0
0
0
0
Figure 15-13. BDLC Control Register 2 (BCR2)
Bit 0
TMIFR0
0
This register controls transmitter operations of the BDLC.
ALOOP — Analog Loopback Mode Bit
This bit determines if the J1850 bus is driven by the analog physical interface’s
final drive stage. The programmer places the transceiver into loopback mode
Data Sheet
250
Byte Data Link Communications (BDLC)
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Go to: www.freescale.com
M68HC12B Family — Rev. 9.0
MOTOROLA