M68HC128 Datasheet, PDF (218/362 Pages) Motorola, Inc – Microcontrollers

Serial Interface
Freescale Semiconductor, Inc.
SWOM — Port S Wired-OR Mode Bit
Controls not only SPI output pins but also the general-purpose output pins
(PS4–PS7) which are not used by SPI.
0 = SPI and/or PS4–PS7 output buffers operate normally.
1 = SPI and/or PS4–PS7 output buffers behave as open-drain outputs.
MSTR — SPI Master/Slave Mode Select Bit
0 = Slave mode
1 = Master mode
CPOL and CPHA — SPI Clock Polarity, Clock Phase Bits
These two bits are used to specify the clock format to be used in SPI operations.
When the clock polarity bit is cleared and data is not being transferred, the SCK
pin of the master device is low. When CPOL is set, SCK idles high. See Figure
14-12 and Figure 14-13.
SSOE — Slave Select Output Enable Bit
The SS output feature is enabled only in master mode by asserting the SSOE
and DDS7.
LSBF — SPI LSB First Enable Bit
0 = Data is transferred most-significant bit (MSB) first.
1 = Data is transferred least-significant bit (LSB) first.
Normally, data is transferred MSB first. This bit does not affect the position of
the MSB and LSB in the data register. Reads and writes of the data register
always have MSB in bit 7.
14.3.5.2 SPI Control Register 2
Address: $00D1
Bit 7
Read: 0
Write:
Reset: 0
6
5
0
0
0
0
= Unimplemented
4
3
2
0
PUPS
RDS
0
1
0
1
Bit 0
0
SPC0
0
0
Figure 14-16. SPI Control Register 2 (SP0CR2)
Read: Anytime
Write: Anytime
PUPS — Pullup Port S Enable Bit
0 = No internal pullups on port S
1 = All port S input pins have an active pullup device. If a pin is programmed
as output, the pullup device becomes inactive.
RDS — Reduce Drive of Port S Bit
0 = Port S output drivers operate normally.
1 = All port S output pins have reduced drive capability for lower power and
less noise.
SPC0 — Serial Pin Control 0 Bit
This bit decides serial pin configurations with MSTR control bit.
Data Sheet
218
Serial Interface
For More Information On This Product,
Go to: www.freescale.com
M68HC12B Family — Rev. 9.0
MOTOROLA