M68HC128 Datasheet, PDF (194/362 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT) Module
13.4.18 Input Control Overwrite Register
Address: $00AA
Bit 7
Read:
NOVW7
Write:
Reset: 0
6
NOVW6
0
5
NOVW5
0
4
NOVW4
0
3
NOVW3
0
2
NOVW2
0
1
NOVW1
0
Figure 13-39. Input Control Overwrite Register (ICOVW)
Read: Anytime
Write: Anytime
Bit 0
NOVW0
0
An IC register is empty when it has been read or latched into the holding register.
A holding register is empty when it has been read.
NOVWx — No Input Capture Overwrite Bits
0 = The contents of the related capture register or holding register can be
overwritten when a new input capture or latch occurs.
1 = The related capture register or holding register cannot be written by an
event unless they are empty (see 13.3.1 IC Channels). This will prevent
the captured value to be overwritten until it is read or latched in the
holding register.
13.4.19 Input Control System Control Register
Address: $00AB
Bit 7
Read:
SH37
Write:
Reset: 0
6
SH26
0
5
SH15
0
4
SH04
0
3
TFMOD
0
2
PACMX
0
1
BUFEN
0
Bit 0
LATQ
0
Figure 13-40. Input Control System Control Register (ICSYS)
Read: Anytime
Write: May be written once (SMODN = 1). Writes are always permitted when
SMODN = 0.
SHxy — Share Input Action of Input Capture Channels x and y Bits
0 = Normal operation
1 = The channel input x causes the same action on the channel y. The port
pin x and the corresponding edge detector is used to be active on the
channel y.
TFMOD — Timer Flag-Setting Mode Bit
Use of the TFMOD bit in the ICSYS register ($AB) in conjunction with the use
of the ICOVW register ($AA) allows a timer interrupt to be generated after
capturing two values in the capture and holding registers instead of generating
an interrupt for every capture.
Data Sheet
194
Enhanced Capture Timer (ECT) Module
For More Information On This Product,
Go to: www.freescale.com
M68HC12B Family — Rev. 9.0
MOTOROLA