M68HC128 Datasheet, PDF (163/362 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Standard Timer Module (TIM)
Block Diagram
12.3.12 Pulse Accumulator Flag Register
Address: $00A1
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
PAOVF PAIF
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 12-25. Pulse Accumulator Flag Register (PAFLG)
Read: Anytime
Write: Anytime
When the TFFCA bit in the TSCR register is set, any access to the PACNT register
clears all the flags in the PAFLG register.
PAOVF — Pulse Accumulator Overflow Flag
Set when the 16-bit pulse accumulator overflows from $FFFF to $0000. This bit
is cleared automatically by a write to the PAFLG register with bit 1 set.
PAIF — Pulse Accumulator Input Edge Flag
Set when the selected edge is detected at the pulse accumulator input pin. In
event mode, the event edge triggers PAIF. In gated time accumulation mode,
the trailing edge of the gate signal at the pulse accumulator input pin triggers
PAIF. This bit is cleared automatically by a write to the PAFLG register with bit
0 set.
12.3.13 16-Bit Pulse Accumulator Count Register
Address: $00A2
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
Address: $00A3
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 12-26. 16-Bit Pulse Accumulator Count Register (PACNT)
Read: Anytime
Write: Anytime
Full count register access should take place in one clock cycle. A separate
read/write for high byte and low byte will give a different result than accessing them
as a word.
M68HC12B Family — Rev. 9.0
MOTOROLA
Standard Timer Module (TIM)
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Go to: www.freescale.com
Data Sheet
163