M68HC128 Datasheet, PDF (180/362 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT) Module
13.4.7 Timer Control Registers
Address: $0088
Bit 7
6
5
4
3
2
1
Bit 0
Read:
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 13-12. Timer Control Register 1 (TCTL1)
NOTE:
Address: $0089
Bit 7
6
5
4
3
2
1
Bit 0
Read:
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 13-13. Timer Control Register 2 (TCTL2)
Read: Anytime
Write: Anytime
OMn Bits — Output Mode
OLn Bits — Output Level
These eight pairs of control bits are encoded to specify the output action to be
taken as a result of a successful OCn compare (see Table 13-1). When either
OMn or OLn is 1, the pin associated with OCn becomes an output tied to OCn
regardless of the state of the associated DDRT bit.
To enable output action by OMn and OLn bits on the timer port, the corresponding
bit in OC7M should be cleared.
Table 13-1. Compare Result Output Action
OMn OLn
Action
0
0 Timer disconnected from output pin logic
0
1 Toggle OCn output line
1
0 Clear OCn output line to 0
1
1 Set OCn output line to 1
To operate the 16-bit pulse accumulators A and B (PACA and PACB)
independently of input capture or output compare 7 and 0, respectively, the user
must set the corresponding bits IOSn = 1, OMn = 0, and OLn = 0. OC7M7 or
OC7M0 in the OC7M register must also be cleared.
Data Sheet
180
Enhanced Capture Timer (ECT) Module
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Go to: www.freescale.com
M68HC12B Family — Rev. 9.0
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