M68HC128 Datasheet, PDF (243/362 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Byte Data Link Communications (BDLC)
BDLC MUX Interface
15.7.4.7 Invalid Active Bit
In Figure 15-8(1), if the active-to-passive received transition beginning the next
data bit (or symbol) occurs between the passive-to-active transition beginning the
current data bit (or symbol) and A, the current bit would be invalid.
15.7.4.8 Valid Active Logic 1
In Figure 15-8(2), if the active-to-passive received transition beginning the next
data bit (or symbol) occurs between A and B, the current bit would be considered
a logic 1.
15.7.4.9 Valid Active Logic 0
In Figure 15-8(3), if the active-to-passive received transition beginning the next
data bit (or symbol) occurs between B and C, the current bit would be considered
a logic 0.
15.7.4.10 Valid SOF Symbol
In Figure 15-8(4), if the active-to-passive received transition beginning the next
data bit (or symbol) occurs between C and D, the current symbol would be
considered a valid SOF symbol.
240 µs
ACTIVE
PASSIVE
(2) VALID BREAK SYMBOL
E
Figure 15-9. J1850 VPW Received BREAK Symbol Times
15.7.4.11 Valid BREAK Symbol
In Figure 15-9, if the next active-to-passive received transition does not occur until
after E, the current symbol is considered a valid BREAK symbol. A BREAK symbol
should be followed by a start-of-frame (SOF) symbol beginning the next message
to be transmitted onto the J1850 bus. See 15.7.2 J1850 Frame Format for BDLC
response to BREAK symbols.
M68HC12B Family — Rev. 9.0
MOTOROLA
Byte Data Link Communications (BDLC)
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Data Sheet
243