M68HC128 Datasheet, PDF (293/362 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
msCAN12 Controller
Programmer’s Model of Control Registers
NOTE:
successfully due to a pending abort request. See 16.12.8 msCAN12
Transmitter Control Register. If not masked, a transmit interrupt is pending
while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx flag. When a TXEx
flag is set, the corresponding ABTRQx bit is cleared. See 16.12.8 msCAN12
Transmitter Control Register.
0 = The associated message buffer is full (loaded with a message due for
transmission).
1 = The associated message buffer is empty (not scheduled).
To ensure data integrity, no registers of the transmit buffers should be written to
while the associated TXE flag is cleared.The CTFLG register is held in the reset
state if the SFTRES bit CMCR0 is set.
16.12.8 msCAN12 Transmitter Control Register
NOTE:
NOTE:
Address: $0107
Bit 7
6
5
4
3
Read: 0
0
ABTRQ2 ABTRQ1 ABTRQ0
Write:
Reset: 0
0
0
0
0
= Unimplemented
2
TXEIE2
0
1
TXEIE1
0
Bit 0
TXEIE0
0
Figure 16-23. msCAN12 Transmitter Control Register (CTCR)
ABTRQ2–ABTRQ0 — Abort Request Bits
The CPU sets an ABTRQx bit to request that a scheduled message buffer
(TXEx = 0) shall be aborted. The msCAN12 grants the request if the message
has not already started transmission, or if the transmission is not successful
(lost arbitration or error). When a message is aborted, the associated TXE and
the abort acknowledge flag (ABTAK) (see 16.12.7 msCAN12 Transmitter Flag
Register) are set and an TXE interrupt is generated if enabled. The CPU cannot
reset ABTRQx. ABTRQx is cleared implicitly whenever the associated TXE flag
is set.
0 = No abort request
1 = Abort request pending
The software must not clear one or more of the TXE flags in CTFGL and
simultaneously set the respective ABTRQ bit(s).
TXEIE2–TXEIE0 — Transmitter Empty Interrupt Enable Bits
0 = No interrupt will be generated from this event.
1 = A transmitter empty (transmit buffer available for transmission) event will
result in a transmitter empty interrupt.
The CTCR register is held in the reset state when the SFTRES bit in CMCR0 is set.
M68HC12B Family — Rev. 9.0
MOTOROLA
msCAN12 Controller
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Data Sheet
293