M68HC128 Datasheet, PDF (138/362 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Pulse-Width Modulator (PWM)
11.2.3 PWM Enable Register
Address: $0042
Bit 7
Read: 0
Write:
Reset: 0
6
5
0
0
0
0
= Unimplemented
4
3
2
1
0
PWEN3 PWEN2 PWEN1
0
0
0
0
Figure 11-6. PWM Enable Register (PWEN)
Bit 0
PWEN0
0
Read: Anytime
Write: Anytime
Setting any of the PWENx bits causes the associated port P line to become an
output regardless of the state of the associated data direction register (DDRP) bit.
This does not change the state of the data direction bit. When PWENx returns to 0,
the data direction bit controls I/O direction. On the front end of the PWM channel,
the scaler clock is enabled to the PWM circuit by the PWENx enable bit being high.
When all four PWM channels are disabled, the prescaler counter shuts off to save
power. There is an edge-synchronizing gate circuit to guarantee that the clock is
only enabled or disabled at an edge.
PWEN3 — PWM Channel 3 Enable Bit
The pulse modulated signal will be available at port P bit 3 when its clock source
begins its next cycle.
0 = Channel 3 disabled
1 = Channel 3 enabled
PWEN2 — PWM Channel 2 Enable Bit
The pulse modulated signal will be available at port P bit 2 when its clock source
begins its next cycle.
0 = Channel 2 disabled
1 = Channel 2 enabled
PWEN1 — PWM Channel 1 Enable Bit
The pulse modulated signal will be available at port P bit 1 when its clock source
begins its next cycle.
0 = Channel 1 disabled
1 = Channel 1 enabled
PWEN0 — PWM Channel 0 Enable Bit
The pulse modulated signal will be available at port P bit 0 when its clock source
begins its next cycle.
0 = Channel 0 disabled
1 = Channel 0 enabled
Data Sheet
138
Pulse-Width Modulator (PWM)
For More Information On This Product,
Go to: www.freescale.com
M68HC12B Family — Rev. 9.0
MOTOROLA