M38002M4 Datasheet, PDF (99/173 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.4 Processor mode
Figure 2.4.4, Figure 2.4.5 and Figure 2.4.6 show a standard timing at 8 MHz (No-Wait).
A0–A7
(Port P0)
A8–A14
(Port P1)
S
(A15)
OE
(RD of 3800)
DQ1–DQ8
(Port P2)
WR
Address (low-order)
Address (high-order)
td(AH—RD)
125 ns - 35 ns (min)
tWL(RD)
125 ns - 10 ns (min)
ta(OE)
50 ns (max)
Data
tsu(DB—RD)
65 ns (min)
“H” level
td(AH—RD)
tWL(RD)
ta(OE)
tsu(DB—RD)
: _{RD delay time after outputting address of 3800}
: RD pulse width of 3800
: Output enabled access time of M5M5256BP
: ^{Data bus setup time before RD of 3800}
Fig. 2.4.4 Read-cycle (OE access, SRAM)
A0–A7
(Port P0)
Address (low-order)
A8–A14
(Port P1)
Address (high-order)
CE
tPHL
5.8 ns (max)
OE
(RD of 3800)
D0–D7
(Port P2)
WR
td(AH—RD)
125 ns - 35 ns (min)
“H” level
tPHL
td(AH— RD)
tWL(RD)
ta(OE)
tsu(DB— RD)
tWL(RD)
125 ns - 10ns (min)
ta(OE)
50 ns (max)
Data
tsu(DB— RD)
65 ns (min)
: Output delay time of 74F04
: RD delay time after outputting address of 3800
: RD pulse width of 3800
: Output enabled access time of M5M27C256AK
: Data bus setup time before RD of 3800
Fig. 2.4.5 Read-cycle (OE access, EPROM)
3800 GROUP USER’S MANUAL
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