M38002M4 Datasheet, PDF (88/173 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.3 Serial I/O
The communication is performed according to the timing shown below. In the slave unit, when a
synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is
processed as the beginning (heading) of a block.
When a clock is input again after one block (8 byte) is received, the clock is ignored.
Figure 2.3.26 shows a setting of related registers.
D0
D1
D2
D7
D0
Byte cycle
Block transfer period
Block transfer cycle
Interval between blocks
Heading adjustive time
Processing for heading adjustment
Fig. 2.3.25 Timing chart [Cyclic transmission or reception of block data between microcomputers]
Master unit
Serial I/O control register (Address : 1A6)
b7
b0
SIOCON 1 1 1 1 1 0 0 0
Slave unit
Serial I/O control register (Address : 1A16)
b7
b0
SIOCON 1 1 1 1 0 1
BRG count source : f(XIN)
Synchronous clock : BRG/4
Not use the SRDY output
Transmit interrupt source :
Transmit shift operating completion
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Serial I/O enabled
Not be effected by external clock
Synchronous clock : External clock
Not use the SRDY output
Not use the serial I/O transmit interrupt
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Serial I/O enabled
Both of units
UART control register (Address : 1B16)
b7
b0
UARTCON
0
P45/TXD pin : CMOS output
Baud rate generator (Address : 1C16)
b7
b0
BRG
7
Set “division ratio – 1”
Fig. 2.3.26 Setting of related registers [Cyclic transmission or reception of block data between
microcomputers]
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3800 GROUP USER’S MANUAL