M38002M4 Datasheet, PDF (9/173 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

List of figures
List of figures
CHAPTER 1 HARDWARE
Fig. 1 Pin configuration of M38002M4-XXXFP/M38003M6-XXXHP ....................................... 1-2
Fig. 2 Pin configuration of M38002M4-XXXSP ......................................................................... 1-3
Fig. 3 Functional block diagram .................................................................................................. 1-4
Fig. 4 Part numbering ................................................................................................................... 1-6
Fig. 5 Memory expansion plan .................................................................................................... 1-7
Fig. 6 Memory expansion plan (Extended operating temperature version) .......................... 1-9
Fig. 7 740 Family CPU register structure ................................................................................ 1-10
Fig. 8 Register push and pop at interrupt generation and subroutine call ........................ 1-11
Fig. 9 Structure of CPU mode register .................................................................................... 1-13
Fig. 10 Memory map diagram .................................................................................................... 1-14
Fig. 11 Memory map of special function register (SFR) ....................................................... 1-15
Fig. 12 Port block diagram (single-chip mode) ....................................................................... 1-17
Fig. 13 Interrupt control .............................................................................................................. 1-19
Fig. 14 Structure of interrupt-related registers ........................................................................ 1-19
Fig. 15 Structure of timer XY register ...................................................................................... 1-20
Fig. 16 Block diagram of timer X, timer Y, timer 1, and timer 2 ........................................ 1-21
Fig. 17 Block diagram of clock synchronous serial I/O ......................................................... 1-22
Fig. 18 Operation of clock synchronous serial I/O function .................................................. 1-22
Fig. 19 Block diagram of UART serial I/O............................................................................... 1-23
Fig. 20 Operation of UART serial I/O function ....................................................................... 1-24
Fig. 21 Structure of serial I/O control registers ...................................................................... 1-25
Fig. 22 Example of reset circuit ................................................................................................ 1-26
Fig. 23 Internal status of microcomputer after reset .............................................................. 1-26
Fig. 24 Timing of reset ............................................................................................................... 1-27
Fig. 25 Ceramic resonator circuit .............................................................................................. 1-28
Fig. 26 External clock input circuit ........................................................................................... 1-28
Fig. 27 Block diagram of clock generating circuit .................................................................................. 1-28
Fig. 28 Memory maps in various processor modes ............................................................... 1-29
Fig. 29 Structure of CPU mode register .................................................................................. 1-29
Fig. 30 ONW function timing ...................................................................................................... 1-30
Fig. 31 Programming and testing of One Time PROM version ........................................... 1-32
Fig. 32 Timing chart after an interrupt occurs ........................................................................ 1-34
Fig. 33 Time up to execution of the interrupt processing routine ....................................... 1-34
CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory map of I/O port related registers ............................................................... 2-2
Fig. 2.1.2 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6, 7) .......................................................... 2-3
Fig. 2.1.3 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6, 7) ........................... 2-3
Fig. 2.2.1 Memory map of timer related registers ..................................................................... 2-5
Fig. 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y .............................................. 2-6
Fig. 2.2.3 Structure of Timer 1 .................................................................................................... 2-6
Fig. 2.2.4 Structure of Timer 2, Timer X, Timer Y................................................................... 2-7
Fig. 2.2.5 Structure of Timer XY mode register ....................................................................... 2-8
Fig. 2.2.6 Structure of Interrupt request register 1 .................................................................. 2-9
3800 GROUP USER’S MANUAL
i