M38002M4 Datasheet, PDF (109/173 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPENDIX
3.1 Electrical characteristics
Table 3.1.10 Timing requirements in memory expansion mode and microprocessor mode (2)
(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Unit
Min. Typ. Max.
tsu(ONW–φ) Before φ ONW input set up time
–20
ns
th(φ–ONW) After φ ONW input hold time
–20
ns
tsu(DB–φ)
Before φ data bus set up time
180
ns
th(φ–DB)
After φ data bus hold time
0
ns
tsu(ONW–RD) Before RD ONW input set up time
tsu(ONW–WR) Before WR ONW input set up time
–20
ns
th(RD–ONW) After RD ONW input hold time
th(WR–ONW) After WR ONW input hold time
–20
ns
tsu(DB–RD)
th(RD–DB)
Before RD data bus set up time
After RD data bus hold time
185
ns
0
ns
Table 3.1.11 Switching characteristics in memory expansion mode and microprocessor mode (2)
(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tc(φ)
twH(φ)
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
td(φ–WR)
tv(φ–WR)
td(φ–DB)
tv(φ–DB)
twL(RD)
twL(WR)
Parameter
φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width
After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
SYNC valid time
RD and WR delay time
RD and WR valid time
After φ data bus delay time
After φ data bus valid time
RD pulse width, WR pulse width
RD pulse width, WR pulse width
(When one-wait is valid)
Test conditions
Fig. 3.1.1
Limits
Min.
Typ.
Unit
Max.
2tc(XIN)
ns
tc(XIN)–20
ns
tc(XIN)–20
ns
150 ns
10
15
ns
150 ns
10
15
ns
40
ns
20
ns
15
25 ns
3
7
15 ns
200 ns
15
ns
tc(XIN)–20
ns
3tc(XIN)–20
ns
td(AH–RD)
td(AH–WR)
After AD15–AD8 RD delay time
After AD15–AD8 WR delay time
tc(XIN)–145
ns
td(AL–RD)
td(AL–WR)
After AD7–AD0 RD delay time
After AD7–AD0 WR delay time
tc(XIN)–145
ns
tv(RD–AH)
tv(WR–AH)
After RD AD15–AD8 valid time
After WR AD15–AD8 valid time
5
10
ns
tv(RD–AL)
tv(WR–AL)
After RD AD7–AD0 valid time
After WR AD7–AD0 valid time
5
10
ns
td(WR–DB)
tv(WR–DB)
After WR data bus delay time
After WR data bus valid time
195 ns
10
ns
td(RESET–RESETOUT) RESETOUT output delay time
tv(φ–RESET) RESETOUT output valid time (Note)
300 ns
0
300 ns
Note: The RESETOUT goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after the RESET
input goes “H”.
3800 GROUP USER’S MANUAL
3-7