M38002M4 Datasheet, PDF (136/173 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPENDIX
3.5 List of registers
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A16]
B
Name
Function
0 INT0 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
1 ^{INT1 interrupt edge}
selection bit
0 : Falling edge active
1 : Rising edge active
2 INT2 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
3 INT3 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
4 INT4 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
5 INT5 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
6 Nothing is allocated for these bits. These are write disabled
7 ^{bits. When these bits are read out, the values are “0.”}
At reset _{R W}
0
0
0
0
0
0
0
!
0
!
Fig. 3.5.12 Structure of Interrupt edge selection register
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register (CPUM) [Adress : 3B16]
B
Name
Function
0 ^{Processor mode bits}
00 : Single-chip mode
01 : Memory expansion mode
1
10 : Microprocessor mode
11 : Not available
2 ^{Stack page selection}
bit
0 : 0 page
1 : 1 page
3 Nothing is allocated for these bits. These are write
4 disabled bits. When these bits are read out, the
5 ^{values are “0.”}
6
7
T An initial value of bit 1 is determined by a level of the CNVSS pin.
At reset R W
0
T
0
!
0
!
0
!
0
!
0
!
0
!
Fig. 3.5.13 Structure of CPU mode register
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3800 GROUP USER’S MANUAL