M38002M4 Datasheet, PDF (30/173 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

HARDWARE
FUNCTIONAL DESCRIPTION
I/O Ports
Direction registers
The 3800 group has 58 programmable I/O pins arranged in eight
I/O ports (ports P0 to P7). The I/O ports have direction registers
which determine the input/output direction of each individual pin.
Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Table 6. List of I/O port functions
Pin
P00 – P07
P10 – P17
P20 – P27
P30 – P37
P40,P41
P42/INT0,
P43/INT1
P44/RXD,
P45/TXD,
P46/SCLK,
P47/SRDY
P50/INT2,
P51/INT3,
P52/INT4,
P53/INT5
P54/CNTR0,
P55/CNTR1
P56,P57
P60 – P67
P70, P71
Name
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Input/Output
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
I/O Format
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
Non-Port Function
Address low-order byte
output
Address high-order
byte output
Data bus I/O
Control signal I/O
Related SFRs
CPU mode register
CPU mode register
CPU mode register
CPU mode register
Ref.No.
(1)
Interrupt edge selection
External interrupt input
(2)
CMOS 3-state output
register
Input/output,
CMOS compatible
(3)
individual bits
Serial I/O control
input level
(4)
Serial I/O function I/O register
(5)
UART control register
(6)
Interrupt edge selection
External interrupt input
(2)
register
CMOS 3-state output
Input/output,
CMOS compatible
individual bits
Timer X and Timer Y
input level
Timer XY mode register
(7)
function I/O
CMOS 3-state output
Input/output,
CMOS compatible
individual bits
(1)
input level
Input/output,
individual bits
CMOS 3-state output
CMOS compatible
input level
Note 1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as func-
tion I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
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3800 GROUP USER’S MANUAL