M38002M4 Datasheet, PDF (48/173 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
The interrupt processing routine begins with the machine cycle fol-
lowing the completion of the instruction that is currently in execu-
tion.
Figure 32 shows a timing chart after an interrupt occurs, and Fig-
ure 33 shows the time up to execution of the interrupt processing
routine.
φ
SYNC
RD
WR
Address bus
PC
S, SPS S-1, SPS S-2, SPS BL BH AL, AH
Data bus
Not used PCH PCL PS AL AH
SYNC : CPU operation code fetch cycle
BL, BH : Vector address of each interrupt
AL, AH : Jump destination address of each interrupt
SPS : “0016” or “0116”
Fig. 32 Timing chart after an interrupt occurs
Generation of interrupt request
Start of interrupt processing
Main routine
Waiting time for
post-processing
of pipeline
Stack push and _{Interrupt processing routine}
Vector fetch
0 to 16^T cycles
2 cycles
5 cycles
7 to 23 cycles
(At performing 8.0 MHz, 1.75 µs to 5.75 µs)
T : at execution of DIV instruction (16 cycles)
Fig. 33 Time up to execution of the interrupt processing routine
1-34
3800 GROUP USER’S MANUAL