M1A3P250-1VQ100I Datasheet, PDF (82/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 Flash Family FPGAs
CLK
Data
CLR
Out_QF
Out_QR
1
2
3
4
5
t_DDRIREMCLR
t_DDRICLR2Q1
t_DDRICLR2Q2
t_DDRICLKQ1
2
3
t_DDRISUD
6
7
t_DDRIHD
8
9
t_DDRIRECCLR
4
6
t_DDRICLKQ2
5
7
Figure 2-20 • Input DDR Timing Diagram
Timing Characteristics
Table 2-102 • Input DDR Propagation Delays
Commercial-Case Conditions: T_J = 70°C, Worst Case VCC = 1.425 V
Parameter
Description
–2
–1 Std. Units
t_DDRICLKQ1
t_DDRICLKQ2
t_DDRISUD
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (Fall)
Data Setup for Input DDR (Rise)
0.27 0.31 0.37 ns
0.39 0.44 0.52 ns
0.25 0.28 0.33 ns
0.25 0.28 0.33 ns
t_DDRIHD
Data Hold for Input DDR (Fall)
Data Hold for Input DDR (Rise)
0.00 0.00 0.00 ns
0.00 0.00 0.00 ns
t_DDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR
0.46 0.53 0.62 ns
t_DDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR
0.57 0.65 0.76 ns
t_DDRIREMCLR Asynchronous Clear Removal time for Input DDR
0.00 0.00 0.00 ns
t_DDRIRECCLR Asynchronous Clear Recovery time for Input DDR
0.22 0.25 0.30 ns
t_DDRIWCLR
Asynchronous Clear Minimum Pulse Width for Input DDR
0.22 0.25 0.30 ns
t_DDRICKMPWH Clock Minimum Pulse Width High for Input DDR
0.36 0.41 0.48 ns
t_DDRICKMPWL Clock Minimum Pulse Width Low for Input DDR
0.32 0.37 0.43 ns
F_DDRIMAX
Maximum Frequency for Input DDR
350 309 263 MHz
Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 15
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