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| M1A3P250-1VQ100I Datasheet, PDF (76/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support | |||
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ProASIC3 Flash Family FPGAs
Table 2-97 ⢠Parameter Definition and Measuring Nodes
Parameter Name
Parameter Definition
tOCLKQ
Clock-to-Q of the Output Data Register
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOSUE
Enable Setup Time for the Output Data Register
tOHE
Enable Hold Time for the Output Data Register
tOCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
tOREMCLR
Asynchronous Clear Removal Time for the Output Data Register
tORECCLR
Asynchronous Clear Recovery Time for the Output Data Register
tOECLKQ
Clock-to-Q of the Output Enable Register
tOESUD
Data Setup Time for the Output Enable Register
tOEHD
Data Hold Time for the Output Enable Register
tOESUE
Enable Setup Time for the Output Enable Register
tOEHE
Enable Hold Time for the Output Enable Register
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
tOEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register
tOERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
tICLKQ
Clock-to-Q of the Input Data Register
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tISUE
Enable Setup Time for the Input Data Register
tIHE
Enable Hold Time for the Input Data Register
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
tIREMCLR
Asynchronous Clear Removal Time for the Input Data Register
tIRECCLR
Asynchronous Clear Recovery Time for the Input Data Register
Note: *See Figure 2-15 on page 2-70 for more information.
Measuring Nodes
(from, to)*
HH, DOUT
FF, HH
FF, HH
GG, HH
GG, HH
LL, DOUT
LL, HH
LL, HH
HH, EOUT
JJ, HH
JJ, HH
KK, HH
KK, HH
II, EOUT
II, HH
II, HH
AA, EE
CC, AA
CC, AA
BB, AA
BB, AA
DD, EE
DD, AA
DD, AA
Revision 15
2- 71
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