M1A3P250-1VQ100I Datasheet, PDF (111/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 Flash Family FPGAs
Table 2-123 • A3P250 FIFO 4k×1 (continued)
Worst Commercial-Case Conditions: T_J = 70°C, VCC = 1.425 V
Parameter
Description
t_RSTAF
t_RSTBQ
RESET Low to Almost Empty/Full Flag Valid
RESET Low to Data Out Low on DO (pass-through)
RESET Low to Data Out Low on DO (pipelined)
t_REMRSTB
t_RECRSTB
t_MPWRSTB
t_CYC
F_MAX
RESET Removal
RESET Recovery
RESET Minimum Pulse Width
Clock Cycle Time
Maximum Frequency
–2
6.13
0.92
0.92
0.29
1.50
0.21
3.23
310
–1
6.98
1.05
1.05
0.33
1.71
0.24
3.68
272
Std.
8.20
1.23
1.23
0.38
2.01
0.29
4.32
231
Units
ns
ns
ns
ns
ns
ns
ns
MHz
Embedded FlashROM Characteristics
CLK
t_SU
t_HOLD
t_SU
t_HOLD
t_SU
t_HOLD
Address
Data
A₀
t_CKQ2
D₀
Figure 2-43 • Timing Diagram
Timing Characteristics
Table 2-124 • Embedded FlashROM Access Time
Parameter
Description
t_SU
t_HOLD
t_CK2Q
F_MAX
Address Setup Time
Address Hold Time
Clock to Out
Maximum Clock Frequency
A₁
t_CKQ2
D₀
t_CKQ2
D₁
–2
0.53
0.00
21.42
15
–1
0.61
0.00
24.40
15
Std.
0.71
0.00
28.68
15
Units
ns
ns
ns
MHz
Revision 15
2- 106