M1A3P250-1VQ100I Datasheet, PDF (197/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

5 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each version of the ProASIC3 datasheet.
Revision
Changes
Page
Revision 15
Added corner pad table note (3) to "QN132 – Bottom View" (SAR 47442).
4-6
(July 2014)
Ambient temperature removed in Table 2-2, table notes and "ProASIC3 Ordering 2-2
Information" figure were modified (SAR 48343).
1-III
Other updates were made to maintain the style and consistency of the datasheet.
NA
Revision 14
(April 2014)
Note added for the discontinuance of QN132 package to the following tables and I, II, 4-6
section: "ProASIC3 Devices", "I/Os Per Package ¹", "ProASIC3 FPGAs Package
Sizes Dimensions" and "QN132 – Bottom View" section (SAR 55118).
Revision 13
(January 2013)
The "ProASIC3 Ordering Information" section has been updated to mention "Y" as
"Blank" mentioning "Device Does Not Include License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43104).
Added a note to Table 2-2 • Recommended Operating Conditions ¹ (SAR 43644):
The programming temperature range supported is T_ambient = 0°C to 85°C.
The note in Table 2-115 • ProASIC3 CCC/PLL Specification referring the reader to
SmartGen was revised to refer instead to the online help associated with the core
(SAR 42569).
1-III
2-2
2-89
Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip NA
(SoC) throughout the document (SAR 40284).
Live at Power-Up (LAPU) has been replaced with ’Instant On’.
Revision 12
The Security section was modified to clarify that Microsemi does not support
1-1
(September 2012) read-back of programmed data.
Added a Note stating "VMV pins must be connected to the corresponding VCCI pins. 2-1
See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information." to _2-2
Table 2-1 • Absolute Maximum Ratings and Table 2-2 • Recommended Operating
Conditions ¹ (SAR 38321).
Table 2-35 • Duration of Short Circuit Event Before Failure was revised to change
the maximum temperature from 110°C to 100°C, with an example of six months
instead of three months (SAR 37933).
2-30
In Table 2-93 • Minimum and Maximum DC Input and Output Levels, VIL and VIH
were revised so that the maximum is 3.6 V for all listed values of VCCI (SAR
28549).
2-67
Figure 2-36 • FIFO Read and Figure 2-37 • FIFO Write are new (SAR 28371).
2-98
The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)" 3-1
section in the "Pin Descriptions" chapter: "Within the package, the VMV plane is
decoupled from the simultaneous switching noise originating from the output buffer
VCCI domain" and replaced with “Within the package, the VMV plane biases the
input stage of the I/Os in the I/O banks” (SAR 38321). The datasheet mentions that
"VMV pins must be connected to the corresponding VCCI pins" for an ESD
enhancement.
Revision 15
5-1