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M1A3P250-1VQ100I Datasheet, PDF (105/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
ProASIC3 Flash Family FPGAs
WCLK
FULL
AFULL
tCYC
tCKAF
tWCKFF
WA/RA
(Address Counter)
NO MATCH
NO MATCH
Figure 2-40 • FIFO FULL Flag and AFULL Flag Assertion
Dist = AFF_TH
MATCH (FULL)
WCLK
WA/RA MATCH
(Address Counter) (EMPTY)
NO MATCH
RCLK
1st Rising
Edge
After 1st
Write
NO MATCH
2nd Rising
Edge
After 1st
Write
tRCKEF
EMPTY
NO MATCH
AEMPTY
NO MATCH
Dist = AEF_TH + 1
tCKAF
Figure 2-41 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK
WA/RA
(Address Counter)
WCLK
MATCH (FULL)
NO MATCH
1st Rising
Edge
After 1st
Read
FULL
NO MATCH
1st Rising
Edge
After 2nd
Read
tWCKF
NO MATCH
AFULL
Figure 2-42 • FIFO FULL Flag and AFULL Flag Deassertion
NO MATCH
Dist = AFF_TH – 1
tCKAF
Revision 15
2- 100