M1A3P250-1VQ100I Datasheet, PDF (81/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

DDR Module Specifications
Input DDR Module
Input DDR
ProASIC3 Flash Family FPGAs
Data
INBUF
A
D
Out_QF
(to core)
FF1
B
CLK
CLKBUF
E
Out_QR
(to core)
FF2
C
CLR
INBUF
DDR_IN
Figure 2-19 • Input DDR Timing Model
Table 2-101 • Parameter Definitions
Parameter Name
Parameter Definition
t_DDRICLKQ1
t_DDRICLKQ2
t_DDRISUD
t_DDRIHD
t_DDRICLR2Q1
t_DDRICLR2Q2
t_DDRIREMCLR
t_DDRIRECCLR
Clock-to-Out Out_QR
Clock-to-Out Out_QF
Data Setup Time of DDR input
Data Hold Time of DDR input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
Clear Recovery
Measuring Nodes (from, to)
B, D
B, E
A, B
A, B
C, D
C, E
C, B
C, B
Revision 15
2- 76