M1A3P250-1VQ100I Datasheet, PDF (69/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-88 • 3.3 V PCI/PCI-X
Commercial-Case Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Speed Grade t_DOUT
Std.
0.66
t_DP
2.68
t_DIN
0.04
t_PY t_EOUT t_ZL
0.86 0.43 2.73
t_ZH
1.95
t_LZ
3.21
t_HZ
3.58
t_ZLS
4.97
t_ZHS Units
4.19 ns
–1
0.56 2.28 0.04 0.73 0.36 2.32 1.66 2.73 3.05 4.22 3.56 ns
–2
0.49 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.68 3.71 3.13 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-89 • 3.3 V PCI/PCI-X
Commercial-Case Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Speed Grade t_DOUT
Std.
0.66
t_DP
2.31
t_DIN
0.04
t_PY t_EOUT t_ZL
0.85 0.43 2.35
t_ZH
1.70
t_LZ
2.79
t_HZ
3.22
t_ZLS
4.59
t_ZHS Units
3.94 ns
–1
0.56 1.96 0.04 0.72 0.36 2.00 1.45 2.37 2.74 3.90 3.35 ns
–2
0.49 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by Microsemi Designer software when
the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-11. The
building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
FPGA
OUTBUF_LVDS
Bourns Part Number: CAT16-LV4F12
P
165 
P
Z₀ = 50 
140 
100 
165 
N
Z₀ = 50 
N
Figure 2-11 • LVDS Circuit Diagram and Board-Level Implementation
FPGA
+
–
INBUF_LVDS
Revision 15
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