M1A3P250-1VQ100I Datasheet, PDF (25/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 Flash Family FPGAs
Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
Applicable to Standard I/O Banks
Equiv.
Software
Default
Drive
Drive Strength Slew Min.
I/O Standard Strength Option² Rate V
VIL
Max.
V
VIH
VOL
Min.
V
Max.
V
Max.
V
VOH
Min.
V
IOL¹ IOH¹
mA mA
3.3 V LVTTL / 8 mA 8 mA High –0.3
0.8
3.3 V
LVCMOS
2
3.6
0.4
2.4
88
3.3 V
100 µA 8 mA High –0.3
0.8
LVCMOS
Wide Range³
2
3.6
0.2
VCCI – 0.2 0.1 0.1
2.5 V
LVCMOS
8 mA 8 mA High –0.3
0.7
1.7
2.7
0.7
1.7
88
1.8 V
LVCMOS
4 mA 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6
0.45 VCCI – 0.45 4 4
1.5 V
LVCMOS
2 mA 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2
Notes:
1. Currents are measured at 85°C junction temperature.
2. 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the
equivalent software default drive strength. These values are for Normal Ranges ONLY.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
Table 2-21 • Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial and Industrial Conditions
Commercial¹
IIL³
IIH⁴
Industrial²
IIL³
IIH⁴
DC I/O Standards
µA
µA
µA
µA
3.3 V LVTTL / 3.3 V LVCMOS
10
10
15
15
3.3 V LVCMOS Wide Range
10
10
15
15
2.5 V LVCMOS
10
10
15
15
1.8 V LVCMOS
10
10
15
15
1.5 V LVCMOS
10
10
15
15
3.3 V PCI
10
10
15
15
3.3 V PCI-X
10
10
15
15
Notes:
1. Commercial range (0°C < T_A < 70°C)
2. Industrial range (–40°C < T_A < 85°C)
3. IIL is the input leakage current per I/O pin over recommended operation conditions where
–0.3V < V_IN <V_IL.
4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
Revision 15
2- 20