M1A3P250-1VQ100I Datasheet, PDF (78/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

Output Register
ProASIC3 Flash Family FPGAs
CLK
Data_out
50%
1
50%
50%
t_OSUD t_OHD
50%
0
50%
50%
t_OCKMPWH t_OCKMPWL
50%
50%
50%
Enable
Preset
Clear
50%
t_OHE
t_OSUE
t_OWPRE t_ORECPRE
50%
50%
t_OWCLR ^tORECCLR
50%
50%
t_OREMPRE
50%
t_OREMCLR
50%
DOUT
t_OPRE2Q
50%
50%
t_OCLR2Q
t_OCLKQ
50%
Figure 2-17 • Output Register Timing Diagram
Timing Characteristics
Table 2-99 • Output Data Register Propagation Delays
Commercial-Case Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2 –1 Std. Units
t_OCLKQ
Clock-to-Q of the Output Data Register
0.59 0.67 0.79 ns
t_OSUD
Data Setup Time for the Output Data Register
0.31 0.36 0.42 ns
t_OHD
Data Hold Time for the Output Data Register
0.00 0.00 0.00 ns
t_OSUE
Enable Setup Time for the Output Data Register
0.44 0.50 0.59 ns
t_OHE
Enable Hold Time for the Output Data Register
0.00 0.00 0.00 ns
t_OCLR2Q Asynchronous Clear-to-Q of the Output Data Register
0.80 0.91 1.07 ns
t_OPRE2Q Asynchronous Preset-to-Q of the Output Data Register
0.80 0.91 1.07 ns
t_OREMCLR Asynchronous Clear Removal Time for the Output Data Register
0.00 0.00 0.00 ns
t_ORECCLR Asynchronous Clear Recovery Time for the Output Data Register
0.22 0.25 0.30 ns
t_OREMPRE Asynchronous Preset Removal Time for the Output Data Register
0.00 0.00 0.00 ns
t_ORECPRE Asynchronous Preset Recovery Time for the Output Data Register
0.22 0.25 0.30 ns
t_OWCLR
Asynchronous Clear Minimum Pulse Width for the Output Data Register
0.22 0.25 0.30 ns
t_OWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 ns
t_OCKMPWH Clock Minimum Pulse Width High for the Output Data Register
0.36 0.41 0.48 ns
t_OCKMPWL Clock Minimum Pulse Width Low for the Output Data Register
0.32 0.37 0.43 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 15
2- 73