M1A3P250-1VQ100I Datasheet, PDF (77/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

Input Register
CLK
Data
50%
1
50%
50%
t_ISUD ^tIHD
50%
0
50%
50%
ProASIC3 Flash Family FPGAs
t_ICKMPWH t_ICKMPWL
50%
50%
50%
Enable
Preset
50%
t_IHE
t_ISUE
t_IWPRE t_IRECPRE
50%
50%
t_IWCLR
t_IRECCLR
t_IREMPRE
50%
t_IREMCLR
Clear
Out_1
50%
50%
t_IPRE2Q
50%
t_ICLKQ
50%
t_ICLR2Q
50%
50%
Figure 2-16 • Input Register Timing Diagram
Timing Characteristics
Table 2-98 • Input Data Register Propagation Delays
Commercial-Case Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2 –1 Std. Units
t_ICLKQ
Clock-to-Q of the Input Data Register
0.24 0.27 0.32 ns
t_ISUD
Data Setup Time for the Input Data Register
0.26 0.30 0.35 ns
t_IHD
Data Hold Time for the Input Data Register
0.00 0.00 0.00 ns
t_ISUE
Enable Setup Time for the Input Data Register
0.37 0.42 0.50 ns
t_IHE
Enable Hold Time for the Input Data Register
0.00 0.00 0.00 ns
t_ICLR2Q Asynchronous Clear-to-Q of the Input Data Register
0.45 0.52 0.61 ns
t_IPRE2Q Asynchronous Preset-to-Q of the Input Data Register
0.45 0.52 0.61 ns
t_IREMCLR Asynchronous Clear Removal Time for the Input Data Register
0.00 0.00 0.00 ns
t_IRECCLR Asynchronous Clear Recovery Time for the Input Data Register
0.22 0.25 0.30 ns
t_IREMPRE Asynchronous Preset Removal Time for the Input Data Register
0.00 0.00 0.00 ns
t_IRECPRE Asynchronous Preset Recovery Time for the Input Data Register
0.22 0.25 0.30 ns
t_IWCLR
Asynchronous Clear Minimum Pulse Width for the Input Data Register
0.22 0.25 0.30 ns
t_IWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data Register
0.22 0.25 0.30 ns
t_ICKMPWH Clock Minimum Pulse Width High for the Input Data Register
0.36 0.41 0.48 ns
t_ICKMPWL Clock Minimum Pulse Width Low for the Input Data Register
0.32 0.37 0.43 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 15
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