DDP3310B Datasheet, PDF (49/60 Pages) Micronas – Display and Deflection Processor

ADVANCE INFORMATION
DDP 3310B
4.6.4.7. Horizontal and Vertical Sync Inputs and Clock and Freqency Select Pins
Symbol
V_IL
V_IH
C_IN
Parameter
Input Low Voltage
Input High Voltage
Input Capacitance
t_IS
Input Setup Time
t_IH
Input Hold Time
Pin Name Min.
HS
−
VS
VS2
2.0
CM0
CM1
−
FREQSEL
HS
6
VS
VS2
7
Typ.
−
−
5
−
−
Max.
0.8
−
−
Unit Test Conditions
V
V
pF
−
ns
−
ns
V_IH
LLC1
t_IH
V_IL
t_IS
HS, VS, VS2 Inputs
V_IH
V_IL
Fig. 4–23: Sync Inputs referenced to line-locked clock
4.6.4.8. Horizontal Flyback Input
Symbol
V_IL
V_IH
V_IHST
Parameter
Input Low Voltage
Input High Voltage
Input Hysteresis
Pin Name Min.
HFLB
−
2.6
0.1
Typ.
−
−
−
Max.
1.8
−
−
Unit Test Conditions
V
V
V
4.6.4.9. FIFO Control Signals
Symbol
V_OL
Parameter
Output Low Voltage
V_OH
Output High Voltage
t_OT
Output Transition Time
I_OL
Output Current
Pin Name Min.
Typ.
FIFORRD −
−
FIFORD
FIFORWR _{VSUPP −}
FIFOWR − 0.4
−
10
−10
−
Max. Unit
0.4
V
VSUPP V
20
ns
10
mA
Test Conditions
I_OL = 1.6 mA
I²C[PSTSY] = 6
−I_OL = 1.6 mA
I²C[PSTSY] = 6
C_LOAD = 30pF
I²C[PSTSY] = 6
Micronas
49