DDP3310B Datasheet, PDF (46/60 Pages) Micronas – Display and Deflection Processor

DDP 3310B
ADVANCE INFORMATION
4.6.4.2. Line-locked Clock Inputs: LLC1, LLC2 (see Fig. 4–21)
Symbol
V_IL
V_IH
t_SK
t_R, t_F
C_IN
1/T_LLC1
t_WL1
t_WH1
1/T_LLC2
t_WL2
t_WH2
Parameter
Input Low Voltage
Input High Voltage
Clock skew
Clock Rise / Fall Time
Input Capacitance
Clock Frequency
Clock Low Time
Clock High Time
Clock Frequency
Clock Low Time
Clock High Time
Pin Name Min.
LLC1
−
LLC2
2.0
−
−
−
LLC1
12.0
26
26
LLC2
25.1
7
7
Typ.
−
−
−
−
5
−
−
−
−
−
−
Max.
0.8
−
±6
5
−
17.2
−
43.3
−
−
Unit
V
V
ns
ns
pF
MHz
ns
ns
MHz
ns
ns
Test Conditions
4.6.4.3. Luma, Chroma Inputs (see Fig. 4–21)
Symbol
V_IL
V_IH
t_IS
t_IH
C_IN
Parameter
Input Low Voltage
Input High Voltage
Input Setup Time
Input Hold Time
Input Capacitance
Pin Name Min.
Y[0...7]
−
C[0...7]
2.0
7
6
−
Typ.
−
−
−
−
5
Max.
0.8
−
−
−
−
Unit Test Conditions
V
V
ns
ns
pF
LLC1
LLC2
Y,C Inputs
t_WH1
T_LLC1
t_WL1
t_R1
t_SK ^tF1
t_SK
T_LLC2
t_WH2
t_WL2
t_R2
t_F2
t_IS
t_IH
V_IH
V_IL
Fig. 4–21: Line-locked clock input pins and luma/chroma bus input timing
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V_IH
V_IL
V_IH
V_IL
Micronas