DDP3310B Datasheet, PDF (30/60 Pages) Micronas – Display and Deflection Processor

DDP 3310B
ADVANCE INFORMATION
Table 3–3: Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr. Mode Function
Default Name
DISPLAY FREQUENCY DOUBLING
h’176
16-r/w
display frequency doubling control word
bit[1:0]
display raster mode (A’ = field A in raster B)
0 = A A‘ B‘ B
1=AA B B
2 = A A B‘ B‘
3=not used
bit[3:2]
minimum field length filter
0 = off
1 = 2 fields
2 = 3 fields
3 = 4 fields
bit[5:4]
input sync doubling switch
0 = leave H and V sync unchanged
1 = double VSYNC and leave HSYNC unchanged
2 = double HSYNC and leave VSYNC unchanged
3 = double H and V sync
bit[6]
clock switch
0 = Clock from LLC2 pin divided by 2
1 = Clock from LLC1 pin
bit[7]
test bit, set to 0
bit[8]
0
1
automatic VS/VS2 polarity detection
Low-active VS/VS2 input
bit[9]
0/1
High/Low-active HS input
bit[10]
0/1
VS / VS2 Pin is source of VSYNC
bit[11]
0/1
dis-/enable still picture (only available if
display frequency doubling is enabled)
bit[12]
0/1
High / Low-active FIFO controll signals
DFDCTRL
0 DFDMODE
0 DFDFILT
0 DFDSW
0 DFDCLK
0
0 VSYPOL
0 HSYPOL
0 VSYSRC
0 STILL
0 FIFOPOL
TIMING
h’1A4
16-r/w vertical blanking start
bit [8:0] 0..511 first line of vertical blanking (+ 128 offset)
182 VBST
h’1A0
16-r/w vertical blanking stop
bit [8:0] 0..511 last line of vertical blanking
22 VBSO
h’1D3
16-r/w bit[10:0] 0..1295 horizontal blanking start
(see Table 2–5 for max. pixels per line)
253 HBST
h’1D4
16-r/w bit[10:0] 0..1295 horizontal blanking stop
(see Table 2–5 for max. pixels per line)
331 HBSO
h’1D2
16-r/w bit[10:0]
0..1295
Start at active video relative to pixel
counter.
(see Table 2–5 for max. pixels per line)
330 NEWLIN
h’18b
16-r/w bit [8:0] 0...511
start point of active video relative to incom-
ing HS signal in steps of 2 LLC2 clocks; can
be used e.g. for panning
0 SFIF
30
Micronas