DDP3310B Datasheet, PDF (23/60 Pages) Micronas – Display and Deflection Processor

ADVANCE INFORMATION
DDP 3310B
Table 3–2: I²C Control Registers
I²C Control and Status Registers
Subaddr. Mode Function
Default Name
XDFP INTERFACE
h’13
16-w XDFP read address
bit[[9:0]
10-bit XDFP RAM address
bit[15:10] 0
reserved, set to zero
DFPRD
h’12
16-w XDFP write address
bit[[9:0]
10-bit XDFP RAM address
bit[15:10]
reserved, set to zero
DFPWR
ANALOG FAST-BLANK MONITOR
h’1E
8-r
Fast-Blank signal status
bit[0]
0/1
FBLIN level Low/High
bit[1]
FBLIN slope: 1 = falling edge occurred
bit[7:2]
not used
FBLSTAT
FBLEV
FBSLO
h’11
16-r/w picture frame color, 12 bit wide
bit[3:0] 0..15
blue amplitude
bit[7:4] 0..15
green amplitude
bit[11:8] 0..15
red amplitude
bit[15:12] 0
not used
PFC
0 PFCB
0 PFCG
0 PFCR
0
OUTPUT PINS
h’10
8-r/w output pin configuration
bit[2:0]
pin driver strength, FIFO control
7 = output tristate
6 = minimum strength
0 = maximum strength
bit[3]
0/1
strong/weak driver strength PWM1
bit[4]
0/1
strong/weak driver strength PWM2
bit[5]
0/1
disable/enable internal resistor for vertical
and East/West drive output
bit[6]
0/1
High/Low-active horizontal flyback input
bit[7]
0/1
disable/enable following I/O pin:
FIFO -controll signals, PWM1&2, HCS,
R/G/BIN2, and VS2.
PSTR
0 PSTSY
0 PSTPR1
0 PSTPR2
0 VEWXR
0 FLYPOL
0 OSDOFF
Micronas
23