DDP3310B Datasheet, PDF (22/60 Pages) Micronas – Display and Deflection Processor

DDP 3310B
ADVANCE INFORMATION
3.3. XDFP Control and Status Registers
The second class are “XDFP-REGISTERS”, which are
used by the XDFP on-chip controller. Access to these
registers is achieved by subaddressing.
– Writing to these registers is done by sending the
device write address first, followed by the XDFP-
write subaddress, two address bits for the desired
XDFP-register, and the two data bytes.
– For reading, the XDFP-register address has to be
transmitted first by sending the device write
address, followed by the XDFP-read subaddress
and the two XDFP-register address bytes. Without
sending a stop condition, reading of the addressed
data is done by sending the device read address
and reading two bytes of data.
Fig. 3–3 shows I²C protocol for read and write opera-
tions. Table 3–3 gives definitions of the XDFP control
and status registers. If these registers are smaller than
16 bit, the remaining bits should be 0 on write and read
operations. Due to the internal architecture, the IC can-
not react immediately to an I²C request, which inter-
acts with the on-chip controller. The maximum
response timing is approximately 20 ms. If the
addressed controller is not ready for further transmis-
sions on the I²C-bus, the clock line SCL is pulled low.
This puts the current transmission into a wait state.
After a certain period of time, the clock line will be
released and the interrupted transmission is carried
on.
A hardware reset initializes all control registers to 0.
The automatic chip initialization loads a selected set of
registers with the default values given in Table 3–3.
Table 3–1: XDFP read/write address
XDFP Read address
h’13
XDFP Write address
h’12
The register modes are
8/16- bit width
r read only register
w write only register
r/w write/read data register
Note: set unused bits to ‘0‘!
The mnemonics used in the DDP 3310B demo soft-
ware are given in the last column.
Write to XDFP Control Register:
S 1000101 W Ack XDFP Write Addr. Ack High-Byte Addr. Ack Low-Byte Addr. Ack High-Byte data Ack Low-Byte Data Ack P
Read from XDFP Control Register:
S 1000101 W Ack XDFP Read Addr. Ack High-Byte Addr. Ack Low-Byte Addr. Ack S 1000101 R Ack High-Byte Data Ack Low-Byte Data Nak P
W ⁼ 0 (Write Bit)
R ⁼ 1 (Read Bit)
S ⁼ Start Condition
P ⁼ Stop Condition
Ack = 0 (Acknowledge Bit from DDP 3310B=gray
or Controller = hatched)
Nak = 1 (Not Acknowledge Bit from Controller=hatched or
indicating an error state from DDP 3310B=gray)
Fig. 3–3: XDFP protocol
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Micronas