DDP3310B Datasheet, PDF (42/60 Pages) Micronas – Display and Deflection Processor

DDP 3310B
ADVANCE INFORMATION
4.5. Pin Circuits
VSUPD
P
N
GNDD
Fig. 4–3: Input pins 3, 12, 13, 14, 43 to 50, 54 to 61,
63, and 64 (VS2, FREQSEL, CM1, CM0, C[7:0],
Y[7:0], HS, VS)
VSUPP
P
N
GNDP
Fig. 4–4: Output pins 4 to 7
(FIFORRD, FIFORD, FIFOWR, FIFORWR)
N
GNDP
Fig. 4–5: Output pin 8 (HOUT)
V_REF
Fig. 4–6: Input pins 9 to 11
(HFLB, SAFETY, VPROT)
N
GNDO
Fig. 4–8: Output pin 15 (RSW2)
P
to ADC _N
N
VSUPO
Fig. 4–9: Input/Output pin 16 (RSW1)
P
N
Fig. 4–10: Input pin 17 (SENSE)
PP
VSUPO
P
Flyback
-
+
VEWXR
N
N
N
GNDO
Fig. 4–11: Output pins 19 and 20 (VERT+, VERT−)
V_REF
Fig. 4–7: Input pins 30 and 34
(FBLIN1, FBLIN2)
42
Micronas