DDP3310B Datasheet, PDF (33/60 Pages) Micronas – Display and Deflection Processor

ADVANCE INFORMATION
DDP 3310B
Table 3–3: Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr. Mode Function
ANALOG RGB INSERTION
h’17A
16-r/w
Fast-Blank interface mode
bit [0]
0
1
Fast-Blank from FBLIN1 pin
force internal Fast-Blank signal to High
bit [1]
0/1
Fast-Blank active High/Low at FBLIN pin
bit [2]
0
1
Fast-Blank from FBLIN1 pin
force internal Fast-Blank signal to Low
bit[3]
0
1
Fast-Blank priority
FBLIN1>FBLIN2
FBLIN1<FBLIN2
bit [4]
0
1
Fast-Blank from FBLIN2 pin
force internal Fast-Blank signal to Low
bit [5]
0
1
Fast-Blank from FBLIN2 pin
force internal Fast-Blank signal to High
bit[6]
0/1
Fast-Blank monitor input select FBLIN1/2
bit[7]
0/1
disable/enable clamping for RGBIN1&2
bit[8]
0/1
half contrast signal active High/Low
at HCS pin
bit[9]
0/1
disable/enable half contrast switching
bit[10]
0
1
half contrast signal from HCS pin
force internal half contrast signal to High
bit[11]
0
1
clamp RGBIN1 to black (if CLAMP =1)
clamp RGBIN1 to bias (if CLAMP =1)
bit[12]
0
1
clamp RGBIN2 to black (if CLAMP =1)
clamp RGBIN2 to bias (if CLAMP =1)
I²C-CONTROLLED 8-BIT PWM
h’178
16-r/w bit[7:0] 0..255
PWM1 data word
h’179
16-r/w bit[7:0] 0..255
PWM2 data word
XDFP STATUS REGISTER
h’0
16-r/w firmware version number
bit[7:0]
firmware release
bit[15:8]
hardware version number (TC)
Default Name
FBLMODE
0 FBFOH1
0 FBPOL
0 FBFOL1
0 FBPRIO
0 FBFOL2
0 FBFOH2
0 FBMON
0 CLAMP
0 HCSPOL
0 HCSEN
0 HCSFOH
0 C1_B
0 C2_B
0 PWM1
0 PWM2
VER
− FW_REL
− HW_VER
Micronas
33