DDP3310B Datasheet, PDF (43/60 Pages) Micronas – Display and Deflection Processor

ADVANCE INFORMATION
DDP 3310B
VSUPO
P
P
VEWXR
N
GNDO
Fig. 4–12: Output pin 21 (EW)
VSUPO
VRD/BCS
+
-
int. ref.
voltage
ref. current
XREF
GNDO
Fig. 4–13: Input pins 22 and 29 (XREF, VDR/BCS)
N
Bias
N
GNDO
Fig. 4–14: Output pins 23 to 26
(SVM, ROUT, GOUT, BOUT)
VSUPD
P
N
GNDD
Fig. 4–17: Output pins 40 and 41 (PWM1, PWM2)
VSUPO
P
N
GNDO
Fig. 4–18: Input pin 42 (HCS)
N
XTAL1
VSUPD
P
XTAL2
N
P
GNDD
Fig. 4–19: Input pin 66 (XTAL1), Output pin 65 (XTAL2)
Clamping
N
N
GNDO
Fig. 4–15: Input pins 31 to 33 and 35 to 37
(R/G/BIN1, R/G/BIN2)
N
GNDD
Fig. 4–20: Input/Output pins 67 and 68 (SDA, SCL)
Fig. 4–16: Input pins 38, 39, 53, and 62
(TEST, RESQ, LLC2, LLC1)
Micronas
43