DDP3310B Datasheet, PDF (41/60 Pages) Micronas – Display and Deflection Processor

ADVANCE INFORMATION
4.4. Pin Configuration
VSUPP
GNDP
VS2
FIFORRD
FIFORD
FIFOWR
FIFORWR
HOUT
HFLB
SCL
SDA
XTAL1
XTAL2
VS
HS
LLC1
Y7
SAFETY
VPROT
FREQSEL
CM1
CM0
RSW2
RSW1
SENSE
GNDM
VERT+
VERT−
EW
XREF
SVM
ROUT
GOUT
BOUT
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
DDP 3310B
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Y6
Y5
Y4
Y3
Y2
Y1
Y0
LLC2
GNDD
VSUPD
C7
C6
C5
C4
C3
C2
C1
GNDO
VSUPO
VRD/BCS
FBLIN1
RIN1
GIN1
BIN1
FBLIN2
C0
HCS
PWM2
PWM1
RESQ
TEST
BIN2
GIN2
RIN2
Fig. 4–2: 68-pin PLCCK package
DDP 3310B
Micronas
41