DDP3310B Datasheet, PDF (25/60 Pages) Micronas – Display and Deflection Processor

ADVANCE INFORMATION
DDP 3310B
Table 3–3: Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr. Mode Function
CHROMA CHANNEL
h’1AF
16-r/w
luma/chroma matching delay
bit [2:0] −2...2
variable chroma delay
bit [3]
not used, set to “0”
bit [4]
0/1
bit [5]
C_B (U) sample first / C_R (V) sample first
not used, set to “0”
h’1AB
16-r/w
digital transient improvement
bit [3:0] 0..15
coring value
bit [7:4] 0..15
DTI gain
bit [8]
0/1
narrow/wide bandwidth mode
LUMA CHANNEL
h’1B1
16-r/w bit [14:9] 0..63
picture contrast in steps of 1/32
h’19A
16-r/w bit [8:0] −256..255 luma DC-offset
h’1AA
16-r/w
luma peaking filter, the gain at high frequencies and small
signal amplitudes is: 1 + (k1+k2)/8
bit [3:0] 0..15
k1: peaking level undershoot
bit [7:4] 0..15
k2: peaking level overshoot
bit [8]
0/1
peaking value normal/inverted
(peaking/softening)
h’1AE
16-r/w
luma peaking filter, coring
bit [4:0] 0..31
coring level
bit [7:5]
000
001
01x
100
101
11x
peaking reduction
100 %
80 %
60 %
50 %
40 %
30 %
bit [8]
0/1
peaking filter center frequency High/Low
h’18A
16-r/w
luma soft limiter, slope A and B
bit [3:0]
slope segment A
bit [7:4]
slope segment B
h’18E
16-r/w
luma soft limiter, limit A
bit [7:0]
luma soft limiter absolute limit (unsigned)
bit [8]
0/1
modulation off/on
(resolution enhancement)
h’192
16-r/w
luma soft limiter, limit B
bit [8:0]
luma soft limiter segment B tilt point
(unsigned)
h’196
16-r/w bit [8:0]
luma soft limiter segment A tilt point
(unsigned)
Default Name
CRCTRL
0 CDEL
0
0 ENVU
DTICTRL
1 DTICO
5 DTIGA
1 DTIMO
32 CTM
0 BRM
PK1
4 PKUN
4 PKOV
0 PKINV
PK2
3 COR
0 PKRD
0 PFS
LSLS
0 LSLSA
0 LSLSB
LSLA
255 LSLAL
0 LSLM
300 LSLTB
250 LSLTA
Micronas
25