DDP3310B Datasheet, PDF (20/60 Pages) Micronas – Display and Deflection Processor

DDP 3310B
ADVANCE INFORMATION
2.3.10. Display Frequency Doubling
The DDP 3310B handles single or double vertical and
horizontal input frequencies. The Display Frequency
Doubling is used when single H/V frequencies are
applied and a FIFO for video frequency doubling is
used. In this mode it is mandatory to supply an active
video signal to the HS pin, which is not vertical
blanked.
Three different raster modes are selectable via I2C
bus:
A A‘ B‘ B (reduced line flicker)
A A B B (improved vertical resolution)
A A B‘ B‘ (non-interlaced)
A/B means field A/B in original raster position and A‘/B‘
means field A/B in the opposite raster position.
A minimum field length filter can be switched on (DFD-
FILT) to write only the smallest field length of the past
up to four fields into the memory. This prevents read-
before-write errors in signals with a strong changing
field length (e.g. VCR signals).
2.3.11. General-purpose D/A Converter
There are two D/A converters realized as pulse width
modulators. The resolution is 8 bit and the clock fre-
quency is 20.25 MHz. The outputs are push-pull types.
For a ripple-free output voltage, a first-order low-pass
filter with a corner frequency <120 Hz should be
applied. The D/A converters will be adjusted via I²C-
bus. They can be used to adjust two DC voltages, for
example for horizontal raster position, raster tilt, or just
as switching outputs when the values 0 and 255 are
selected.
2.3.12. Clock and Reset
The DDP 3310B has the capability to accept different
line-locked clock rates: 27, 32, and 40.5 MHz.This
external clock rate is converted internally to a clock
rate of 40.5 or 40 MHz by means of a PLL. Selection of
external clock frequency is done with pins CM1 and
CM0. See Table 2–6 for clock frequency selection. To
ensure lock of PLL a reset pulse of at least 500 µs
must be applied after power-up.
Table 2–6: Clock Frequency Selection
CM1
0
0
1
CM0
0
1
0
LLC2
27 MHz
32 MHz
40.5 MHz
2.3.13. Reset and Power-On
The IC has its own voltage supervision to generate an
internal reset during power on or when the supply volt-
age (VSUPD) goes below ~4.5V. Also, a clock supervi-
sion of the 5-MHz clock keeps the internal reset active
until a proper clock signal is detected (e.g. three clock
cycles with the correct period). When the reset pin
RESQ or the internal reset becomes active, all
counters and registers are set to zero. When the reset
pins are released, the internal reset is still active for
approximately 4 µs. Then all registers are loaded with
their default values listed in Table 3–3. This initializa-
tion takes about 100 µs. During and after reset, the
HOUT signal remains High until a soft start (see Sec-
tion 2.3.3.) will be performed by setting RAMP_EN.
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