DDP3310B Datasheet, PDF (31/60 Pages) Micronas – Display and Deflection Processor

ADVANCE INFORMATION
DDP 3310B
Table 3–3: Control Registers of the XDFP, continued
XDFP Control and Status Registers
Subaddr. Mode Function
Default Name
HORIZONTAL DEFLECTION
h’1D1
16-r/w bit [5:0] 20..35
horizontal drive pulse duration (High time)
30 HDRV
h’140
16-r/w
horizontal deflection control register
bit [0]
0
reserved, set to 0
bit [1]
0/1
enable/disable vertical protection
bit [2]
0/1
enable/disable H-safety protection
bit [3]
0/1
disable/enable drive high during flyback
bit [4]
1
start ramp up/down
bit [7:5] 0..7
000
001
010
100
101
110
horizontal frequency
H-Freq. pixels per line @LLC
in kHz
27 MHz
32 MHz
31.25
864
1024
35.1
768
912
31.46
858
1024
33.8
800
944
37.5
720
852
37.9
712
844
HCTRL
0
0 VPROT_DIS
0 HPROT_DIS
0 EFLB
0 RAMP_EN
0 HFREQ
h’141
16-r/w
adjustable delay of PLL2, clamping, and blanking (relative to
incoming hsync) adjust clamping pulse for analog RGB input
bit [15:1] Range ±600, 1 step = 1 pixel clock
5 POFS2
h’144
16-r/w
adjustable delay of flyback, H/VSYNC and analog RGB (rela-
tive to PLL2) adjust horizontal drive or H/VSYNC
bit [15:1] Range ±600, 1 step = 1 pixel clock
0 POFS3
h’145
h’142
16-r/w
PLL2/3 filter coefficients
bit [14:6] 0...511 proportional coefficient PLL3, c*2^−9
bit [14:6] 0...511 proportional coefficient PLL2, c*2^−9
102 PKP3
184 PKP2
h’14A
16-r/w bit[15:6] −512...511 vertical angle
0 ANGLE
h’14B
16-r/w bit[15:6] −512...511 vertical bow
0 BOW
VERTICAL MODES
h’1E2
16-r/w bit [0]
0/1
VSYNC synchronized/ free running
0 VS_MODE
h’1E3
16-r/w
raster mode
bit [1:0] 0
1
2
3
same input and output raster
field 2 is delayed (only A raster is written)
field 1 is delayed (only B raster is written)
not used
0 R_MODE
h’1E8
16-r/w bit [0]
0/1
automatic lines-per-field adaption (constant
raster amplitude) off/on
0 VA_MODE
Micronas
31