DDP3310B Datasheet, PDF (24/60 Pages) Micronas – Display and Deflection Processor

DDP 3310B
ADVANCE INFORMATION
Table 3–3: Control Registers of the XDFP
XDFP Control and Status Registers
Subaddr. Mode Function
Default Name
INPUT FORMATTER
h’1B0
16-r/w
Input format
bit [0]
0/1
bit [1]
0/1
bit [2]
0/1
bit [4:3] 0...3
4:2:2 / 4:1:1 mode
binary offset / 2‘s complement
enable / disable blanking to black ( for luma
and chroma input when HS = 0 )
select color multiplex
INFMT
1 M411
1 COB
1 BLNK
0 CMUX
SCALER CONTROL REGISTER
h’1C1
16-r/w
scaler mode register
bit[1:0]
scaler mode
0
linear scaling mode
1
non-linear scaling mode, ’panorama’
2
non-linear scaling mode, ’waterglass’
3
reserved
bit[2]
reserved, set to 0
bit[13:3]
reserved, set to 0
bit[14]
0
scaler update command, set to 1 to update
only scaler mode register
bit[15]
0
scaler update command, set to 1 to update
all scaler control registers
0 SCMODE
PANO
0 SCMODUP
0 SCUPDATE
h’1C2
16-r/w
active video length for 1-h FIFO
bit[11:0] 0...1295 length in pixels
720
LLC mode (864/h)
720 FFLIM
h’1C3
16-r/w
scaler1 coefficient; this scaler compresses the signal.
bit[11:0]
1024..4095 compression by a factor c,
the value c*1024 is required
1024 SCINC1
h’1C4
16-r/w
scaler2 coefficient; this scaler expands the signal.
bit[11:0] 256..1024 expansion by a factor c,
the value 1/c*1024 is required
682 SCINC2
h’1C5
16-r/w bit[11:0] 0...4095 scaler1/2 non-linear scaling coefficient
0 SCINC
h’1C6
...
h’1CA
16-r/w
scaler1 window controls (see Table 3–4)
bit[11:0] 0...4095 5 registers for control of the non-linear
scaling
0 SCW1_1
... ...
0 SCW1_5
h’1CB
...
h’1CF
16-r/w
scaler2 window controls (see Table 3–4)
bit[11:0] 0...4095 5 registers for control of the non-linear
scaling
0 SCW2_1
... ...
0 SCW2_5
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Micronas