DDP3310B Datasheet, PDF (38/60 Pages) Micronas – Display and Deflection Processor

DDP 3310B
ADVANCE INFORMATION
4.3. Pin Description
Pin 1 – Supply Voltage, Output Pin Driver VSUPP*
This pin is used as supply for the following digital out-
put pins: FIFORRD, FIFORD, FIFOWR, FIFORWR.
Pin 2 – Ground, Output Pin Driver GNDP*
Output Pin Driver Reference
Pin 3 – Sync Signal Input VS2 (Fig. 4–3)
Additional pin for the vertical sync information. Via I²C-
Register the used vertical sync can be switched
between the inputs VS2 and VS (Pin 64)
Pin 4 – Reset for FIFO Read Counter FIFORRD
(Fig. 4–4)
This signal is active-High and resets the read counter
in the display frequency doubling FIFO.
Pin 5 – Read Enable for FIFO FIFORD (Fig. 4–4)
This signal is active-High and enables the read counter
in the display frequency doubling FIFO.
Pin 6 – Write Enable for FIFO FIFOWR (Fig. 4–4)
This signal is active-High and enables the write
counter in the display frequency doubling FIFO.
Pin 7 – Reset for FIFO Write Counter FIFORWR (Fig.
4–4)
This signal is active-High and resets the write counter
in the display frequency doubling FIFO.
Pin 8 – Horizontal Drive HOUT (Fig. 4–5)
This open-drain output supplies the drive pulse for the
horizontal output stage. A pull-up resistor has to be
used (see Section 2.3.).
Pin 9 – Horizontal Flyback Input HFLB (Fig. 4–6)
Via this pin, the horizontal flyback pulse is supplied to
the DDP 3310B (see Section 2.3.).
Pin 10 – Safety Input SAFETY (Fig. 4–6)
This input has two thresholds. A signal between the
lower and upper threshold means normal function.
Other signals are detected as malfunction (see Section
2.3.9.).
Pin 11 – Vertical Protection Input VPROT (Fig. 4–7)
The vertical protection circuitry prevents the picture
tube from burn-in in the event of a malfunction of the
vertical deflection stage. If the peak-to-peak value of
the vertical sawtooth signal is too small, the RGB out-
put signals are blanked (see Section 2.3.9.).
Pin 12 – H-Drive Frequency Range Select FREQSEL
(Fig. 4–3)
This pin selects the frequency range for the horizontal
drive signal (see Section 2.3.2.).
Pin 13 – Clock Select 40.5 or 27/32 MHz CM1
(Fig. 4–3)
Low level selects 27/32 MHz, High level selects
40.5 MHz (see Section 2.3.12.).
Pin 14 – Clock Select 27 or 32 MHz CM0 (Fig. 4–3)
Low level selects 27 MHz, High level selects 32 MHz
(see Section 2.3.12.).
Pin 15 – Range Switch2 for Measuring ADC RSW2
(Fig. 4–8)
This pin is an open-drain pull-down output. During cut-
off measurement the switch is off. During white drive
measurement the switch is on. Also during the rest of
time it is on. (see Section 2.2.4.).
Pin 16 – Range Switch1 or Second Input for Measur-
ing ADC RSW1 (Fig. 4–9)
This pin is an open-drain pull-down output. During cut-
off and white-drive measurement, the switch is off.
During the rest of time it is on. The RSW1 pin can be
used as second measurement ADC input (see Section
2.2.4.).
Pin 17 – Measurement ADC Input SENSE (Fig. 4–10)
This is the input of the analog to digital converter for
the picture and tube measurement. Three measure-
ment ranges are selectable with RSW1 and RSW2
(see Section 2.2.4.).
Pin 18 – Measurement ADC Reference Input MGND
This is the ground reference for the measurement
A/D converter.
Pin 19 – Vertical Sawtooth Output VERT+ (19)
(Fig. 4–11)
This pin supplies the drive signal for the vertical output
stage. The drive signal is generated with 15-bit preci-
sion. The analog voltage is generated by a 4-bit cur-
rent DAC with external resistor (6 kΩ for proper opera-
tion) and uses digital noise-shaping.
Pin 20 – Vertical Sawtooth Output inverted VERT−
(Fig. 4–11)
This pin supplies the inverted signal of VERT+.
Together with this pin, it can be used to drive symmet-
rical deflection amplifiers.
Pin 21 – East/West Parabola Output EW (Fig. 4–12)
This pin supplies the parabola signal for the East/West
correction. The drive signal is generated with 15-bit
precision. The analog voltage is generated by a 4-bit
current DAC with external resistor and uses digital
noise-shaping.
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Micronas