DDP3310B Datasheet, PDF (11/60 Pages) Micronas – Display and Deflection Processor

Y
C_rC_b
4:2:2/4:1:1
Line-locked
Clock
27/32 MHz
FIFO
Read Ctrl
H/V
FIFO
Write Ctrl
SDA/
SCL
5 MHz
CLK
13.5/16 MHz
27/32 MHz
40.5/40.0 MHz
digital/analog
FI-
FO
Intpl. FI-
4:2:2 _FO
Cock
Generator
Display
Frequency
Doubling
I²C
Inter-
face
Clk
Security
Scaler ^FI-
1
FO
Scaler ^FI-
1
FO
int. H/V
H-Drive
Gen.
Scaler
2
Scaler
2
Contrast
Y _Peaking
Soft Limiter
Cr
Intpl.
CTI
4:4:4
Cb
dig. Bright.
Y _digital R,G,B
RGB
Cr Matrix
Satu-
ration
Cb
White-Dr.
× BCL
Scan.
Vel. Mod.
DAC
R,G,B
Picture
Frame
Gen.
H&V
Timing
3×DAC
RGB
3×DAC
int. Bright.
×White-Drive
R,G,B
DAC DAC
cutoff black
XDFP
– H-PLL2/3, flyback control
and soft start/stop
– vertical, E/W deflection
with EHT compensation
and vertical zoom
– beam current limiter
– cutoff & drive control loop
H/V
Protection
H-Flyb.
Skew
2×DAC
V, E/W
3×DAC
ext. Bright.
×White-Drive
R,G,B
Measu-
rement
ADC
3×DAC
ext. Contr.
× White-drive
× BCL
FBL
Prio
Clamp-
ing
Clamp-
ing
SVM
RGB
out
FBL 1/2
in
RGB1
in
RGB2
in
HDrive
H/V Prot.
Fig. 2–7: Detailed block diagram of the DDP 3310B
H-Flyb
V & E/W Sense RSW1&2