MT40A1G8WE-083E Datasheet, PDF (73/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Write Leveling
Procedure Description
The memory controller initiates the leveling mode of all DRAM by setting bit 7 of MR1
to 1. When entering write leveling mode, the DQ pins are in undefined driving mode.
During write leveling mode, only the DESELECT command is supported, other than
MRS commands to change the Qoff bit (MR1[A12]) and to exit write leveling (MR1[A7]).
Upon exiting write leveling mode, the MRS command performing the exit (MR1[A7] = 0)
may also change the other MR1 bits. Because the controller levels one rank at a time,
the output of other ranks must be disabled by setting MR1 bit A12 to 1. The controller
may assert ODT after ^tMOD, at which time the DRAM is ready to accept the ODT signal,
unless DODTLon or DODTLoff have been altered (the ODT internal pipe delay is in-
creased when increasing WRITE latency [WL] or READ latency [RL] by the previous MR
command), then ODT assertion should be delayed by DODTLon after ^tMOD is satisfied,
which means the delay is now ^tMOD + DODTLon.
The controller may drive DQS_t LOW and DQS_c HIGH after a delay of ^tWLDQSEN, at
which time the DRAM has applied ODT to these signals. After ^tDQSL and ^tWLMRD, the
controller provides a single DQS_t, DQS_c edge, which is used by the DRAM to sample
CK driven from the controller. ^tWLMRD (MAX) timing is controller dependent.
The DRAM samples CK status with the rising edge of DQS and provides feedback on all
the DQ bits asynchronously after ^tWLO timing. There is a DQ output uncertainty of
t_{WLOE defined to allow mismatch on DQ bits. The} t_{WLOE period is defined from the}
transition of the earliest DQ bit to the corresponding transition of the latest DQ bit.
There are no read strobes (DQS_t, DQS_c) needed for these DQs. The controller sam-
ples incoming DQ and either increments or decrements DQS delay setting and launch-
es the next DQS pulse after some time, which is controller dependent. After a 0-to-1
transition is detected, the controller locks the DQS delay setting, and write leveling is
achieved for the device. The following figure shows the timing diagram and parameters
for the overall write leveling procedure.
Figure 18: Write Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2)
CK_c⁵
CK_t
Command MRS²
ODT
diff_DQS⁴
Late Prime DQ¹
DES³
DES
DES
t_MOD
t_WLDQSEN
t_WLMRD
T1
t_WLH
t_WLS
T2
t_WLH
t_WLS
DES
DES
DES NOP DES
DES
DES
t_DQSL6
t_DQSH6
t_DQSL6
t_WLO
t_DQSH6
t_WLO
Early Prime DQ¹
t_WLO
t_WLOE
t_WLO
DES
DES
t_WLOE
Undefined Driving Mode Time Break
Notes: 1. The device drives leveling feedback on all DQs.
2. MRS: Load MR1 to enter write leveling mode.
Don’t Care
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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