MT40A1G8WE-083E Datasheet, PDF (70/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Write Leveling
After the device has been successfully placed in self refresh mode and ^tCKSRE/
t_{CKSRE_PAR have been satisfied, the state of the clock becomes a "Don’t Care." Follow-}
ing a "Don’t Care," changing the clock frequency is permissible, provided the new clock
frequency is stable prior to ^tCKSRX. When entering and exiting self refresh mode for the
sole purpose of changing the clock frequency, the self refresh entry and exit specifica-
tions must still be met as outlined in SELF REFRESH Operation.
For the new clock frequency, additional MRS commands to MR0, MR2, MR3, MR4, MR5,
and MR6 may need to be issued to program appropriate CL, CWL, gear-down mode,
READ and WRITE preamble, Command Address Latency, and ^tCCD_L/^tDLLK values.
When the clock rate is being increased (faster), the MR settings that require additional
clocks should be updated prior to the clock rate being increased. In particular, the PL
latency must be disabled when the clock rate changes, for example, while in self refresh
mode. For example, if changing the clock rate from DDR4-2133 to DDR4-2933 with CA
parity mode enabled, MR5[2:0] must first change from PL = 4 to PL = disable prior to PL
= 6. The correct procedure would be to (1) change PL = 4 to disable via MR5 [2:0], (2)
enter self refresh mode, (3) change clock rate from DDR4-2133 to DDR4-2933, (4) exit
self refresh mode, (5) Enable CA parity mode setting PL = 6 vis MR5 [2:0].
If the MR settings that require different clocks are updated after the clock rate has been
changed, for example. after exiting self refresh mode, the required MR settings must be
updated prior to removing the DRAM from the IDLE state, unless the DRAM is RESET. If
the DRAM leaves the IDLE state to enter self refresh mode or ZQ calibration, the updat-
ing of the required MR settings may be deferred to the next time the DRAM enters the
IDLE state.
If MR6 is issued prior to self refresh entry for new the ^tDLLK value, DLL will relock auto-
matically at self refresh exit. However, if MR6 is issued after self refresh entry, MR0 must
be issued to reset the DLL.
The device input clock frequency can change only within the minimum and maximum
operating frequency specified for the particular speed grade. Any frequency change be-
low the minimum operating frequency would require the use of DLL-on mode to DLL-
off mode transition sequence (see DLL-On/Off Switching Procedures).
Write Leveling
For better signal integrity, DDR4 memory modules use fly-by topology for the com-
mands, addresses, control signals, and clocks. Fly-by topology has benefits from the re-
duced number of stubs and their length, but it also causes flight-time skew between
clock and strobe at every DRAM on the DIMM. This makes it difficult for the controller
to maintain ^tDQSS, ^tDSS, and ^tDSH specifications. Therefore, the device supports a
write leveling feature to allow the controller to compensate for skew. This feature may
not be required under some system conditions, provided the host can maintain the
t_DQSS, t_{DSS, and} t_{DSH specifications.}
The memory controller can use the write leveling feature and feedback from the device
to adjust the DQS (DQS_t, DQS_c) to CK (CK_t, CK_c) relationship. The memory con-
troller involved in the leveling must have an adjustable delay setting on DQS to align the
rising edge of DQS with that of the clock at the DRAM pin. The DRAM asynchronously
feeds back CK, sampled with the rising edge of DQS, through the DQ bus. The controller
repeatedly delays DQS until a transition from 0 to 1 is detected. The DQS delay estab-
lished though this exercise would ensure the ^tDQSS specification. Besides ^tDQSS, ^tDSS
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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