MT40A1G8WE-083E Datasheet, PDF (248/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Synchronous ODT Mode
Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based
on the power-down definition, these modes include the following:
• Any bank active with CKE HIGH
• Refresh with CKE HIGH
• Idle mode with CKE HIGH
• Active power-down mode (regardless of MR1 bit A10)
• Precharge power-down mode
In synchronous ODT mode, R_TT(NOM) will be turned on DODTLon clock cycles after
ODT is sampled HIGH by a rising clock edge and turned off DODTLoff clock cycles after
ODT is registered LOW by a rising clock edge. The ODT latency is determined by the
programmed values for: CAS WRITE latency (CWL), additive latency (AL), and parity la-
tency (PL), as well as the programmed state of the preamble.
ODT Latency and Posted ODT
The ODT latencies for synchronous ODT mode are summarized in the table below. For
details, refer to the latency definitions.
Table 73: ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200
Applicable when write CRC is disabled
Symbol
Parameter
DODTLon
Direct ODT turn-on latency
DODTLoff
Direct ODT turn-off latency
RODTLoff READ command to internal ODT turn-off
latency
RODTLon4 READ command to R_TT(Park) turn-on la-
tency in BC4-fixed
RODTLon8 READ command to R_TT(Park) turn-on la-
tency in BL8/BC4-OTF
ODTH4
ODT Assertion time, BC4 mode
ODTH8
ODT Assertion time, BL8 mode
1^tCK Preamble
CWL + AL + PL - 2
CWL + AL + PL - 2
CL + AL + PL - 2
RODTLoff + 4
RODTLoff + 6
4
6
2^tCK Preamble
CWL + AL + PL - 3
CWL + AL + PL - 3
CL + AL + PL - 3
RODTLoff + 5
RODTLoff + 7
5
7
Unit
t_CK
Timing Parameters
In synchronous ODT mode, the following parameters apply:
• DODTLon, DODTLoff, RODTLoff, RODTLon4, RODTLon8, and ^tADC (MIN)/(MAX).
• ^tADC (MIN) and ^tADC (MAX) are minimum and maximum R_TT change timing skew
between different termination values. These timing parameters apply to both the syn-
chronous ODT mode and the data termination disable mode.
When ODT is asserted, it must remain HIGH until minimum ODTH4 (BC = 4) or
ODTH8 (BL = 8) is satisfied. If write CRC mode or 2^tCK preamble mode is enabled,
ODTH should be adjusted to account for it. ODTHx is measured from ODT first regis-
tered HIGH to ODT first registered LOW or from the registration of a WRITE command.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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