MT40A1G8WE-083E Datasheet, PDF (260/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Electrical Characteristics – AC and DC Single-Ended Input Measurement
Levels
RESET_n Input Levels
Table 83: RESET_n Input Levels (CMOS)
Parameter
AC input high voltage
DC input high voltage
DC input low voltage
AC input low voltage
Rising time
RESET pulse width after power-up
RESET pulse width during power-up
Symbol
V_{IH(AC)_RESET}
V_{IH(DC)_RESET}
V_{IL(DC)_RESET}
V_{IL(AC)_RESET}
t_{R_RESET}
t_{PW_RESET_S}
t_{PW_RESET_L}
Min
0.8 × V_DD
0.7 × V_DD
V_SS
V_SS
–
1
200
Max
V_DD
V_DD
0.3 × V_DD
0.2 × V_DD
1
–
–
Unit
V
V
V
V
μs
μs
μs
Note
1
2
3
4
5
6, 7
6
Notes:
1. Overshoot should not exceed the V_IN shown in the Absolute Maximum Ratings table.
2. After RESET_n is registered HIGH, the RESET_n level must be maintained above
V_{IH(DC)_RESET}, otherwise operation will be uncertain until it is reset by asserting RESET_n
signal LOW.
3. After RESET_n is registered LOW, the RESET_n level must be maintained below V_{IL(DC)_RE-}
SET ^{during tPW_RESET, otherwise the DRAM may not be reset.}
4. Undershoot should not exceed the V_IN shown in the Absolute Maximum Ratings table.
5. Slope reversal (ring-back) during this level transition from LOW to HIGH should be miti-
gated as much as possible.
6. RESET is destructive to data contents.
7. See RESET Procedure at Power Stable Condition figure.
Figure 204: RESET_n Input Slew Rate Definition
V_{IH(AC)_RESET,min}
V_{IH(DC)_RESET,min}
t_{PW_RESET}
V_{IL(DC)_RESET,max}
V_{IL(AC)_RESET,max}
Command/Address Input Levels
t_{R_RESET}
Table 84: Command and Address Input Levels: DDR4-1600 Through DDR4-2400
Parameter
AC input high voltage
Symbol
V_IH(AC)
Min
V_REF + 100
Max
V_DD5
Unit
mV
Note
1, 2, 3
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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