MT40A1G8WE-083E Datasheet, PDF (120/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Connectivity Test Mode
Connectivity Test Mode
Connectivity test (CT) mode is similar to boundary scan testing but is designed to sig-
nificantly speed up the testing of electrical continuity of pin interconnections between
the device and the memory controller on the PC boards. Designed to work seamlessly
with any boundary scan device, CT mode is supported in all ×4, ×8, and ×16 devices (JE-
DEC states CT mode for ×4 and ×8 is not required on 4Gb and is an optional feature on
8Gb and above).
Contrary to other conventional shift-register-based test modes, where test patterns are
shifted in and out of the memory devices serially during each clock, the CT mode allows
test patterns to be entered on the test input pins in parallel and the test results to be
extracted from the test output pins of the device in parallel. These two functions are al-
so performed at the same time, significantly increasing the speed of the connectivity
check. When placed in CT mode, the device appears as an asynchronous device to the
external controlling agent. After the input test pattern is applied, the connectivity test
results are available for extraction in parallel at the test output pins after a fixed propa-
gation delay time.
Note: A reset of the device is required after exiting CT mode (see RESET and Initializa-
tion Procedure).
Pin Mapping
Only digital pins can be tested using the CT mode. For the purposes of a connectivity
check, all the pins used for digital logic in the device are classified as one of the follow-
ing types:
• Test enable (TEN): When asserted HIGH, this pin causes the device to enter CT mode.
In CT mode, the normal memory function inside the device is bypassed and the I/O
pins appear as a set of test input and output pins to the external controlling agent.
Additionally, the device will set the internal V_REFDQ to V_DDQ × 0.5 during CT mode
(this is the only time the DRAM takes direct control over setting the internal V_REFDQ).
The TEN pin is dedicated to the connectivity check function and will not be used dur-
ing normal device operation.
• Chip select (CS_n): When asserted LOW, this pin enables the test output pins in the
device. When de-asserted, these output pins will be High-Z. The CS_n pin in the de-
vice serves as the CS_n pin in CT mode.
• Test input: A group of pins used during normal device operation designated as test
input pins. These pins are used to enter the test pattern in CT mode.
• Test output: A group of pins used during normal device operation designated as test
output pins. These pins are used for extraction of the connectivity test results in CT
mode.
• RESET_n: This pin must be fixed high level during CT mode, as in normal function.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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