MT40A1G8WE-083E Datasheet, PDF (305/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Current Specifications – Measurement Conditions
Figure 238: Measurement Setup and Test Load for I_DDx, I_DDPx, and I_DDQx
I_DD
I_PP
I_DDQ
V_DD
V_PP
RESET_n
CK_t/CK_c
DDR4
CKE
SDRAM
CS_n
C
ACT_n, RAS_n, CAS_n, WE_n
V_DDQ
DQS_t, DQS_c
DQ
DM_n
A, BG, BA
ODT
ZQ
V_SS
V_SSQ
Figure 239: Correlation: Simulated Channel I/O Power to Actual Channel I/O Power
Applic ation-s pe c ific
memory c ha nne l
env ironmen t
I_{DD Q}
tes t loa d
C hanne l I/O
pow er simulation
I_{DD Q}
s im u la tio n
I_{DD Q}
meas ure ment
C orre c tion
C or relation
C hanne l I/O
power number
Note: 1. Supported by I_DDQ measurement.
I_DD Definitions
Table 135: Basic I_DD, I_PP, and I_DDQ Measurement Conditions
Symbol
I_DD0
Description
Operating One Bank Active-Precharge Current (AL = 0)
CKE: HIGH; External clock: On; ^tCK, nRC, nRAS, CL: see the previous table; BL: 8;¹ AL: 0; CS_n: HIGH between
ACT and PRE; Command, address, bank group address, bank address inputs: partially toggling according to the
next table; Data I/O: V_DDQ; DM_n: stable at 0; Bank activity: cycling with one bank active at a time: 0, 0, 1, 1, 2,
2, ... (see the I_DD0 Measurement-Loop Pattern table); Output buffer and R_TT: enabled in mode registers;² ODT
signal: stable at 0; Pattern details: see the I_DD0 Measurement-Loop Pattern table
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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