MT40A1G8WE-083E Datasheet, PDF (209/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
READ Operation
Figure 153: READ (BL8) to WRITE (BL8) with 1^tCK Preamble and CA Parity in Same or Different Bank
Group
T0
T1
T7
T8
T9
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
CK_c
CK_t
Command READ
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
READ to WRITE command delay
= RL +BL/2 - WL + 2 ^tCK
4 Clocks
t_WR
t_WTR
Bank Group
BGa
Address
BGa or
BGb
Address
Parity
Bank
Col n
DQS_t,
DQS_c
DQ
Bank
Col b
RL = 15
t_RPRE
t_RPST
t_WPRE
t_WPST
DO DO DO DO DO DO DO DO
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
WL = 13
DI DI DI DI DI DI DI DI
b b+1 b+2 b+3 b+4 b+5 b+6 b+7
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL = 8, AL = 0, CL = 11, PL = 4, (RL = CL + AL + PL = 15), READ preamble = 1^tCK, CWL = 9,
AL = 0, PL = 4, (WL = CL + AL + PL = 13), WRITE preamble = 1^tCK.
2. DO n = data-out from column n, DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and WRITE command at T8.
5. CA parity = Enable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
209
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.