MT40A1G8WE-083E Datasheet, PDF (32/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
RESET and Initialization Procedure
– The voltage levels on all balls other than V_DD, V_DDQ, V_SS, and V_SSQ must be less
than or equal to V_DDQ and V_DD on one side and must be greater than or equal
to V_SSQ and V_SS on the other side.
– V_TT is limited to 0.76V MAX when the power ramp is complete.
– V_REFCA tracks V_DD/2.
• Condition B:
– Apply V_PP without any slope reversal before or at the same time as V_DD.
– Apply V_DD without any slope reversal before or at the same time as V_DDQ.
– Apply V_DDQ without any slope reversal before or at the same time as V_TT and
V_REFCA.
– The voltage levels on all pins other than V_PP, V_DD, V_DDQ, V_SS, and V_SSQ must be
less than or equal to V_DDQ and V_DD on one side and must be larger than or
equal to V_SSQ and V_SS on the other side.
2. After RESET_n is de-asserted, wait for another 500μs but no longer then 3 seconds
until CKE becomes active. During this time, the device will start internal state ini-
tialization; this will be done independently of external clocks. A reasonable at-
tempt was made in the design to power up with the following default MR settings:
gear-down mode (MR3 A[3]): 0 = 1/2 rate; per-DRAM addressability (MR3 A[4]): 0
= disable; maximum power-down (MR4 A[1]): 0 = disable; CS to command/
address latency (MR4 A[8:6]): 000 = disable; CA parity latency mode (MR5 A[2:0]):
000 = disable. However, it should be assumed that at power up the MR settings are
undefined and should be programmed as shown below.
3. Clocks (CK_t, CK_c) need to be started and stabilized for at least 10ns or 5 ^tCK
(whichever is larger) before CKE goes active. Because CKE is a synchronous signal,
the corresponding setup time to clock (^tIS) must be met. Also, a DESELECT com-
mand must be registered (with ^tIS setup time to clock) at clock edge Td. After the
CKE is registered HIGH after RESET, CKE needs to be continuously registered
HIGH until the initialization sequence is finished, including expiration of ^tDLLK
and ^tZQinit.
4. The device keeps its ODT in High-Z state as long as RESET_n is asserted. Further,
the SDRAM keeps its ODT in High-Z state after RESET_n de-assertion until CKE is
registered HIGH. The ODT input signal may be in an undefined state until ^tIS be-
fore CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal
may be statically held either LOW or HIGH. If R_TT(NOM) is to be enabled in MR1,
the ODT input signal must be statically held LOW. In all cases, the ODT input sig-
nal remains static until the power-up initialization sequence is finished, including
the expiration of ^tDLLK and ^tZQinit.
5. After CKE is registered HIGH, wait a minimum of RESET CKE EXIT time, ^tXPR, be-
fore issuing the first MRS command to load mode register (^tXPR = MAX (^tXS, 5 ×
t_CK).
6. Issue MRS command to load MR3 with all application settings, wait ^tMRD.
7. Issue MRS command to load MR6 with all application settings, wait ^tMRD.
8. Issue MRS command to load MR5 with all application settings, wait ^tMRD.
9. Issue MRS command to load MR4 with all application settings, wait ^tMRD.
10. Issue MRS command to load MR2 with all application settings, wait ^tMRD.
11. Issue MRS command to load MR1 with all application settings, wait ^tMRD.
12. Issue MRS command to load MR0 with all application settings, wait ^tMOD.
13. Issue a ZQCL command to start ZQ calibration.
14. Wait for ^tDLLK and ^tZQinit to complete.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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